Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate and at least one contact plug. The substrate has an epi-layer. The contact plug is formed on the epi-layer and includes a silicide cap disposed on the epi-layer; a conductive pillar disposed on the silicide cap such that the conductive pillar electrically connects to the epi-layer via the silicide cap; and a hybrid liner. The hybrid liner surrounds the conductive pillar and includes a lower portion abutting the silicide cap and having a nitride material and an upper portion abutting the conductive pillar and having an oxidized nitride material. Due to the hybrid liner, a semiconductor structure with increased capacitance and decreased resistivity can be obtained.

Abstract: A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.

Abstract: Embodiments of the present disclosure provide a semiconductor device with backside source/drain contacts formed using a buried source/drain feature and a semiconductor cap layer formed between the buried source/drain feature and a source/drain region. The buried source/drain feature and the semiconductor cap layer enable self-aligned backside source/drain contact and backside isolation. The semiconductor cap layer functions as an etch stop layer during backside contact formation while enabling source/drain region growth without fabrication penalty, such as voids in the source/drain regions.

Abstract: A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region. The contact structure has a first portion and a second portion. The first portion is below the second portion. The second portion extends through the isolating layer and protrudes above the isolating layer. A portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. The semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: A semiconductor device and a method of manufacturing thereof are provided. The method comprises: forming a gate electrode over a substrate; forming source/drain regions beside the gate electrode; forming contact plugs on the source/drain regions; forming a dielectric layer over the contact plugs and the gate electrode; forming first openings and a second opening in the dielectric layer to expose portions of the contact plugs and a portion of the gate electrode respectively; performing a pre-clean process such as applying an ozone-containing source to the exposed portions of the contact plugs and the gate electrode; performing a surface treatment to the first and second openings to passivate sidewalls of the first and second openings; forming a conductive layer to fill the first openings and the second opening in a same deposition process by using a same metal precursor; and performing a planarization process.

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

Abstract: The present disclosure describes a semiconductor device having a dielectric structure between a source/drain (S/D) structure and a contact structure. The semiconductor device includes a S/D structure on a substrate, a dielectric structure on a top surface of the S/D structure, and a S/D contact structure on the S/D structure and the dielectric structure. A portion of the S/D contact structure is in contact with a top surface of the dielectric structure.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

Abstract: An integrated circuit includes a substrate having a semiconductor layer. The integrated circuit includes a transistor. The transistor includes stacked channels above the semiconductor layer, a first source/drain region in contact with the channels, and a second source/drain region in contact with the channels. A backside source/drain contact is positioned in the substrate directly below and electrically coupled to the first source/drain region. A frontside source/drain contact is directly above and electrically coupled to the first source/drain region. A bottom semiconductor structure is positioned below the second source/drain region and in contact with the semiconductor layer.

Abstract: Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.

Abstract: A shower head structure and a plasma processing apparatus are provided. The shower head structure includes a plate body with a first zone and a second zone on a first surface. A plurality of first through holes are in the first zone, each of the first through holes having a diameter uniform with others of the first through holes. A plurality of second through holes are in the second zone. The first zone is in connection with the second zone, and the diameter of each of the first through holes is greater than a diameter of each of the second through holes. A plasma processing apparatus includes the shower head structure is also provided.

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

Abstract: A semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. The semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. The one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. The dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). In particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.

Abstract: Embodiments of the present disclosure are directed to an electrosurgical pencil integrating module and an electrosurgical device possessing module thereof. The electrosurgical device includes an electrosurgical pencil and an integrating module. The electrosurgical pencil includes a working section. A distal end of the working section is a blade portion. The neck portion extends from the adjacent insulating layer of the working section toward the blade portion. The integrating module is used to combine with the electrosurgical pencil. The integrating module further includes an elastic securing tube and a conduit. The elastic securing tube is used for docking and accommodating the working section. The inner diameter of the inlet end of the elastic securing tube is larger than the maximal cross section of the working section. After the working section passes through the elastic securing tube, the position of the neck portion is hold by the internal wall of the elastic securing tube.

Abstract: The present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. The first memory cell comprises a first data storage layer. A second memory cell is adjacent to the first memory cell. A dielectric layer is disposed laterally between the first memory cell and the second memory cell. An air gap is disposed within the dielectric layer. The air gap is spaced laterally between the first memory cell and the second memory cell.

Abstract: The present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. The first memory cell comprises a first data storage layer. A second memory cell is adjacent to the first memory cell. A dielectric layer is disposed laterally between the first memory cell and the second memory cell. An air gap is disposed within the dielectric layer. The air gap is spaced laterally between the first memory cell and the second memory cell.

Abstract: A phase-change material (PCM) switching device includes: a base dielectric layer; a spreader element disposed in the base dielectric layer, wherein the spreader element extends in a first horizontal direction and comprises: a central portion extending in the first horizontal direction and having a first width in a second horizontal direction perpendicular to the first horizontal direction; a first end portion at a first end of the central portion and having a second width in the second horizontal direction; and a second end portion at a second end of the central portion and having a third width in the second horizontal direction, and wherein at least one of the second width and the third width is larger than the first width; a heater element disposed over the spreader element; a thermal barrier element disposed on the heater element; and a PCM layer disposed on the thermal barrier element.

Abstract: A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.