Abstract: A system for providing video playback comprises a processor configured to synchronize clocks on the plurality of devices to a standard time, provide target video playback positions to the plurality of devices, wherein target video playback positions are based at least in part on the timing information, provide one or more locators for video streams to the plurality of devices, monitor playback status for each of the plurality of devices, and for a device, determine whether the playback status for the device indicates that a selected bitrate is too low or too high or that the playback is fast or slow; in response to determining the selected bitrate is too low, indicate to select a higher bitrate for a device; and in response to determining the selected bitrate is too high, indicate to select a lower bitrate for the device.

Abstract: A system for bitrate adaptation for low latency streaming includes an interface and a processor. The interface is configured to receive statistics, wherein the statistics comprise a server latency and a buffer level. The processor is configured to perform a set of checks based at least in part on the statistics, determine a streaming bitrate based at least in part on the set of checks, and indicate the streaming bitrate.

Abstract: A system of video stream transitioning includes an interface and a video stream transitioner. The interface is to receive an indication for changing from a current video stream to a target video stream. The video stream transitioner is to determine key frame information in the target video stream; determine a specific key frame to switch to; and provide a request for target video stream starting at the specific key frame.

Abstract: A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

Abstract: A prototype debugging system controlled by a host processor over a host bus includes: (a) a vector processor interface bus; (b) one or more programmable logic circuits, at least one of which provided to implement: (i) a logic circuit under verification; (ii) one or more programmable embedded debug circuits each receiving a first group of selected signals from the logic circuit under verification and providing control signals for (1) selecting a portion of the first group of selected signals, or (2) affecting the values of a second group of selected signals in the logic circuit under verification based on a portion of the first group of selected signals satisfying a predetermined triggering condition, wherein the programmable embedded debug circuits each including a built-in memory for storing signal vectors, the programmable embedded debug circuits each being configured according to a trigger specification defining one or more trigger states and triggering conditions; and (iii) a local debugging controller th

Abstract: A prototyping system includes (i) a vector processor having an interface for communicating with a host processor and a second interface (e.g., a vector processor bus) for dispatching vectors; (ii) a number of programmable logic circuits each coupled to the second interface to receive the dispatched vectors; and (iii) a compiler for (a) partitioning an electronic circuit into multiple partitions, assigning each partition to one of the programmable logic circuits, (b) providing multiple connections each provided for connecting signals among the partitions, (c) providing in each programmable logic circuit an interface circuit module that manages the connections among partitions using a virtual interconnection technique, and (d) assigning the physical interconnection resources, such as pins of the programmable logic circuits and physical wires on the boards. First and further assigns at least one virtual interconnection (secondary I/O) between partitions to realize the connections among partitions.

Abstract: A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe circuits for accessing internal nodes of the logic circuit; (b) preparing emulation vectors for use in a vector emulation of the logic circuit in the prototyping system; (c) setting one or more vector substitution points; (d) preparing one or more packet vectors at each vector substitution point for replacing emulation vectors in the vector emulation; (e) performing the vector emulation using the emulation vectors until one of the vector substitution points is reached; and (f) substituting packet vectors for the corresponding emulation vectors at vector substitution point and continuing the vector emulation.

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Abstract: Using a vector-based emulation technique, a hardware-based prototyping system reduces time-consuming recompilation and reduces the iteration time for a verification run. The vector-based emulation technique takes advantage of information derived from user-defined probe points, automatically generated probe points and low-latency snapshots. Using a bounded-cycle simulation technique, the hardware-based prototyping system can provide complete or partial simulation traces covering interested signals and can efficiently evaluates assertions. A user is therefore able to debug in a real system test and to identify causes of fault conditions interactively under a controlled vector debugging environment.

Abstract: Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in accordance with the RTL netlist representation of the low power design. The method further includes verifying completeness, compatibility, and consistency of power requirements for the low power design.

Abstract: Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.

Abstract: Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in accordance with the RTL netlist representation of the low power design. The method further includes verifying completeness, compatibility, and consistency of power requirements for the low power design.

Abstract: Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Abstract: A general test application scheme is proposed for existing scan-based BIST architectures. The objective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT). The proposed test scheme divides the entire test process into multiple test sessions. A different number of capture cycles is applied after scanning in a test pattern in each test session to maximize the fault detection for a distinct subset of faults. A procedure is presented to find the optimal number of capture cycles following each scan sequence for every fault. Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT.

Abstract: An almost full-scan method and system for detecting faults in circuits can achieve higher fault coverages and significantly shorter test application time as compared with full-scan techniques. A special flip-flop selection of strategy is further described which permits implementation of the almost full-scan BIST method and system.

Abstract: A test point selection method for scan-based built-in self-test (BIST). The method calculates a hybrid cost reduction (HCR) value as an estimated value of the corresponding actual cost reduction for all nodes in a circuit under test. A test point is then selected having a largest HCR. This iterative process continues until the fault coverage of the circuit under test reaches a desired value or the number of test points selected is equal to a maximum number of test points. In an alternative embodiment, the cost reduction factor is calculated for all nodes in the circuit under test, the HCR is calculated for only a selected set of candidates, and the candidate having the largest HCR is selected as the test point. The test point selection method achieves higher fault coverage results and reduces computational processing relative to conventional selection methods.

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.