Patents by Inventor Huan-Chun Fu

Huan-Chun Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8222800
    Abstract: A stacked-type piezoelectric device includes a stack of piezoelectric layers, plural conductive layers, a first contact hole, a second contact hole, and plural insulating portions. The piezoelectric layers are disposed between the conductive layers. The first and second contact holes penetrate the piezoelectric layers and the conductive layers, and each of first and second contact holes is filled with a conductive material. Every insulating portion is formed at one conductive layer. Two adjacent insulating portions are respectively formed at the outer rims of the first and second contact holes, to electrically isolate the conductive layer (in which the insulating portion is formed) from the conductive material in the contact hole.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 17, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Chih Chen, Tsung-Fu Tsai, Huan-Chun Fu
  • Publication number: 20120133046
    Abstract: A semiconductor structure and a process thereof are provided. The semiconductor structure includes a semiconductor wafer having a first surface and a second surface opposite to the first surface, through silicon vias and a crack stopping slot. The through silicon vias are embedded in the semiconductor wafer and connected between the first surface and the second surface. The crack stopping slot is located in the periphery of the second surface of the semiconductor wafer. The depth of the crack stopping slot is less than or equal to the thickness of the semiconductor wafer. The process firstly provides a semiconductor wafer having through silicon vias. Then, the aforementioned crack stopping slot is formed at a back side of the semiconductor wafer opposite to the first surface. Next, the semiconductor wafer is thinned from the back side to expose a second end of each through silicon via.
    Type: Application
    Filed: March 1, 2011
    Publication date: May 31, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Hsien Chien, John H. Lau, Hsiang-Hung Chang, Huan-Chun Fu, Tzu-Ying Kuo, Wen-Li Tsai
  • Publication number: 20110006645
    Abstract: A stacked-type piezoelectric device includes a stack of piezoelectric layers, plural conductive layers, a first contact hole, a second contact hole, and plural insulating portions. The piezoelectric layers are disposed between the conductive layers. The first and second contact holes penetrate the piezoelectric layers and the conductive layers, and each of first and second contact holes is filled with a conductive material. Every insulating portion is formed at one conductive layer. Two adjacent insulating portions are respectively formed at the outer rims of the first and second contact holes, to electrically isolate the conductive layer (in which the insulating portion is formed) from the conductive material in the contact hole.
    Type: Application
    Filed: February 12, 2010
    Publication date: January 13, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Chih Chen, Tsung-Fu Tsai, Huan-Chun Fu