Patents by Inventor Huan Ke
Huan Ke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240075158Abstract: Provided are a complex of an anti-IL-4R antibody or an antigen-binding fragment thereof, and a medical use thereof. Specifically, provided are a complex of an antibody that specifically binds to IL-4R or an antigen-binding fragment thereof covalently linked to a toxin, a pharmaceutical composition comprising the complex, and a use thereof in the preparation of a drug for treating IL-4R-mediated diseases or disorders, especially a use in the preparation of an anti-cancer drug.Type: ApplicationFiled: December 22, 2021Publication date: March 7, 2024Inventors: Huan WANG, Yuan LIN, Yucheng TANG, Ke KE, Kan LIN, Cheng LIAO
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Patent number: 10599552Abstract: Described herein are systems and methods for distributed concurrency (DC) bug detection. The method includes identifying a plurality of nodes in a distributed computing cluster; identifying a plurality of messages to be transmitted during execution of an application by the distributed computing cluster; determining a set of orderings of the plurality of messages for DC bug detection, the set of orderings determined based upon the plurality of nodes and the plurality of messages; removing a subset of the orderings from the set of orderings based upon one or more of a state symmetry algorithm, a disjoint-update independence algorithm, or a zero-crash-impact reordering algorithm; and performing DC bug detection testing using the set of orderings after the subset of the orderings is removed from the set of orderings.Type: GrantFiled: April 25, 2018Date of Patent: March 24, 2020Inventors: Jeffrey Lukman, Huan Ke, Haryadi Gunawi, Feng Ye, Chen Tian, Shen Chi Chen
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Publication number: 20190332518Abstract: Described herein are systems and methods for distributed concurrency (DC) bug detection. The method includes identifying a plurality of nodes in a distributed computing cluster; identifying a plurality of messages to be transmitted during execution of an application by the distributed computing cluster; determining a set of orderings of the plurality of messages for DC bug detection, the set of orderings determined based upon the plurality of nodes and the plurality of messages; removing a subset of the orderings from the set of orderings based upon one or more of a state symmetry algorithm, a disjoint-update independence algorithm, or a zero-crash-impact reordering algorithm; and performing DC bug detection testing using the set of orderings after the subset of the orderings is removed from the set of orderings.Type: ApplicationFiled: April 25, 2018Publication date: October 31, 2019Inventors: Jeffrey Lukman, Huan Ke, Haryadi Gunawi, Feng Ye, Chen Tian, Shen Chi Chen
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Patent number: 9983042Abstract: An embodiment of the invention provides a liquid-level sensor to detect liquid-level information of a liquid to be tested in a container. The sensor includes an electrode, a sensing circuit, an amplifier and a controller. The electrode is disposed on the outer surface of the container, comprising a first electrode and a second electrode. The sensing circuit is coupled to a first electrode and a second electrode, and receives a clock signal to generate a first voltage signal and a second voltage signal. The amplifier receives the first voltage signal and the second voltage signal to output an output voltage. The controller acquires liquid-level information of the liquid to be tested according to the output voltage and a voltage-volume table.Type: GrantFiled: December 30, 2015Date of Patent: May 29, 2018Assignee: Industrial Technology Research InstituteInventors: Li-Ren Huang, Zen-Dar Hsu, Cheng-Hsun Lin, Huan-Ke Chiu, Cihun-Siyong Gong, Po-Hsun Tu
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Publication number: 20170153139Abstract: An embodiment of the invention provides a liquid-level sensor to detect liquid-level information of a liquid to be tested in a container. The sensor includes an electrode, a sensing circuit, an amplifier and a controller. The electrode is disposed on the outer surface of the container, comprising a first electrode and a second electrode. The sensing circuit is coupled to a first electrode and a second electrode, and receives a clock signal to generate a first voltage signal and a second voltage signal. The amplifier receives the first voltage signal and the second voltage signal to output an output voltage. The controller acquires liquid-level information of the liquid to be tested according to the output voltage and a voltage-volume table.Type: ApplicationFiled: December 30, 2015Publication date: June 1, 2017Inventors: Li-Ren Huang, Zen-Dar Hsu, Cheng-Hsun Lin, Huan-Ke Chiu, Cihun-Siyong Gong, Po-Hsun Tu
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Patent number: 8665014Abstract: An I/Q demodulation apparatus and method with phase scanning are provided. The demodulation apparatus includes a ring oscillator, a first latch unit, a decoding unit, a counter unit, a second latch unit, a first arithmetical unit and a second arithmetical unit. The first latch unit samples phase signals outputted from the ring oscillator. The decoding unit decodes the output of the first latch unit to correspondingly generate fine code of a first, a second, a third and a fourth codes. The counter unit counts the phase signals. The second latch unit samples the output of the counter unit to correspondingly generate coarse code of the first, the second, the third and the fourth codes. The first arithmetical unit performs an addition/subtraction operation by using the first code and the second code. The second arithmetical unit performs the addition/subtraction operation by using the third code and the fourth code.Type: GrantFiled: February 15, 2012Date of Patent: March 4, 2014Assignee: Industrial Technology Research InstituteInventors: Huan-Ke Chiu, Jia-Hung Peng
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Publication number: 20130156135Abstract: An I/Q demodulation apparatus and method with phase scanning are provided. The demodulation apparatus includes a ring oscillator, a first latch unit, a decoding unit, a counter unit, a second latch unit, a first arithmetical unit and a second arithmetical unit. The first latch unit samples phase signals outputted from the ring oscillator. The decoding unit decodes the output of the first latch unit to correspondingly generate fine code of a first, a second, a third and a fourth codes. The counter unit counts the phase signals. The second latch unit samples the output of the counter unit to correspondingly generate coarse code of the first, the second, the third and the fourth codes. The first arithmetical unit performs an addition/subtraction operation by using the first code and the second code. The second arithmetical unit performs the addition/subtraction operation by using the third code and the fourth code.Type: ApplicationFiled: February 15, 2012Publication date: June 20, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Huan-Ke Chiu, Jia-Hung Peng
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Publication number: 20120262228Abstract: A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.Type: ApplicationFiled: June 22, 2012Publication date: October 18, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Horng-Yuan Shih, Kai-Cheung Juang, Wei-Hsien Chen, Huan-Ke Chiu
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Publication number: 20120019314Abstract: A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.Type: ApplicationFiled: August 13, 2010Publication date: January 26, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Horng-Yuan Shih, Kai-Cheung Juang, Wei-Hsien Chen, Huan-Ke Chiu
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Patent number: 8058915Abstract: A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.Type: GrantFiled: August 30, 2009Date of Patent: November 15, 2011Assignee: Industrial Technology Research InstituteInventors: Huan-Ke Chiu, Tzu-Chan Chueh
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Patent number: 8036611Abstract: A phase modulation method with a polar transmitter. A target frequency is first designated by comparing the RF signal with a reference frequency and the phase sample. An oscillator control word is generated based on the target frequency. A digital oscillator can modulate from a first phase to a second phase to synthesize a preliminary RF signal based on the oscillator control word. When the target frequency exceeds the modulation capability of the digital oscillator, the oscillator control word is generated based on the target frequency minus 180 degrees, and the preliminary RF signal is shifted by 180 degrees to be the RF signal having the target frequency. When the target frequency does not exceed the modulation capability of the digital oscillator, the oscillator control word is generated solely based on the target frequency to output the preliminary RF signal to be the RF signal having the target frequency.Type: GrantFiled: May 5, 2009Date of Patent: October 11, 2011Assignee: Industrial Technology Research InstituteInventors: Huan-Ke Chiu, Chun-Jen Chen
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Patent number: 7940127Abstract: An all digital phase lock loop is disclosed, including a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word includes a first tuning word and a second tuning word, where the frequency range of the digitally controlled oscillator, capable to be adjusted by the second tuning word, is broader than that capable to be adjusted by the first tuning word. The phase detector detects a phase error between the variable signal and a reference signal. The phase error is received by the loop filter to output the oscillator tuning word. The loop filter has several stages of the low pass filters and a modification circuit. The modification circuit detects two filter outputs from two low pass filters among the filters and accordingly adjusts the second tuning word.Type: GrantFiled: December 8, 2008Date of Patent: May 10, 2011Assignee: Industrial Technology Research InstituteInventors: Huan-Ke Chiu, Chun-Jen Chen
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Patent number: 7928888Abstract: A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.Type: GrantFiled: December 16, 2009Date of Patent: April 19, 2011Assignee: Industrial Technology Research InstituteInventors: Huan-Ke Chiu, Horng-Yuan Shih, Chiou-Bang Chen, Tzu-Chan Chueh
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Publication number: 20110084863Abstract: A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.Type: ApplicationFiled: December 16, 2009Publication date: April 14, 2011Applicant: Industrial Technology Research InstituteInventors: Huan-Ke Chiu, Horng-Yuan Shih, Chiou-Bang Chen, Tzu-Chan Chueh
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Publication number: 20100327912Abstract: A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.Type: ApplicationFiled: August 30, 2009Publication date: December 30, 2010Applicant: Industrial Technology Research InstituteInventors: Huan-Ke Chiu, Tzu-Chan Chueh
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Publication number: 20100120381Abstract: A phase modulation method with a polar transmitter. A target frequency is first designated by comparing the RF signal with a reference frequency and the phase sample. An oscillator control word is generated based on the target frequency. A digital oscillator can modulate from a first phase to a second phase to synthesize a preliminary RF signal based on the oscillator control word. When the target frequency exceeds the modulation capability of the digital oscillator, the oscillator control word is generated based on the target frequency minus 180 degrees, and the preliminary RF signal is shifted by 180 degrees to be the RF signal having the target frequency. When the target frequency does not exceed the modulation capability of the digital oscillator, the oscillator control word is generated solely based on the target frequency to output the preliminary RF signal to be the RF signal having the target frequency.Type: ApplicationFiled: May 5, 2009Publication date: May 13, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Huan-Ke Chiu, Chun-Jen Chen
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Patent number: 7620140Abstract: A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor.Type: GrantFiled: January 15, 2009Date of Patent: November 17, 2009Assignee: Industrial Technology Research InstituteInventors: Huan-Ke Chiu, Yeong-Lin Yu, Tzu-Yi Yang
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Publication number: 20090256639Abstract: An all-digital phase-locked loop is disclosed. The all-digital phase-locked loop includes a digitally controlled oscillator, a phase detector, a loop filter, and a bandwidth modification unit. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal, wherein the oscillator tuning word includes a first tuning word and a second tuning word respectively to adjust the capacitance of a first capacitor set and the capacitance of a second capacitor set. The phase detector measures a phase error between the variable signal and a reference signal. The loop filter receives the phase error to generate an initial tuning word. The bandwidth modification unit receives the initial tuning word to adjust the initial tuning word to generate the tuning word according to the available usage range of the first capacitor set and the second capacitor set.Type: ApplicationFiled: March 10, 2009Publication date: October 15, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Huan-Ke Chiu, Chun-Jen Chen
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Publication number: 20090168947Abstract: A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor.Type: ApplicationFiled: January 15, 2009Publication date: July 2, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Huan-Ke Chiu, Yeong-Lin Yu, Tzu-Yi Yang
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Patent number: 7551707Abstract: A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor.Type: GrantFiled: December 29, 2007Date of Patent: June 23, 2009Assignee: Industrial Technology Research InstituteInventors: Huan-Ke Chiu, Yeong-Lin Yu, Tzu-Yi Yang