Abstract: An optimization method for an implementation of mel-frequency cepstral coefficients is provided. The optimization method includes the following steps: performing a framing step, including using a 400×16 static random access memory to temporarily store a plurality of sampling points of a sound signal with overlap, and decomposing the sound signal into a plurality of frames. Each of the plurality of frames is 400 of the sampling points, there is an overlapping region between adjacent two of the plurality of frames, and the overlapping region includes 240 of the sampling points. The optimization method further includes performing a windowing step, which includes multiplying each of the plurality of frames by a window function in a bit-level design, and the optimization method includes performing a fast Fourier transform (FFT) step, which includes applying a 512 point FFT on a frame signal to obtain a corresponding frequency spectrum.

Abstract: In a connection reactivation method, a connection of a PDU session established by user equipment on a N3GPP side is reactivated through communications via a 3GPP network. The user equipment accesses both the 3GPP and the N3GPP network and is originally in an idle state on the N3GPP network. An access and mobility management function entity receives a first message from a session management function entity to reactivate the PDU session connection of the user equipment. The access and mobility management function entity sends a second message to the user equipment via the 3GPP access network to instruct the user equipment to reactivate the connection of the PDU session.

Abstract: A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

Abstract: A memory circuit includes a bank of non-volatile memory (NVM) devices, a plurality of high-voltage (HV) drivers, a global HV power switch configured to generate a HV power signal, and a plurality of HV power switches coupled to the global HV switch. A first HV power switch of the plurality of HV power switches is coupled to each HV driver of the plurality of HV drivers, the first HV power switch of the plurality of HV power switches is configured to output a power signal responsive to the HV power signal, and each HV driver of the plurality of HV drivers is configured to output a HV activation signal to a corresponding column of the bank of NVM devices responsive to the power signal.

Abstract: A broadband network gateway (BNG) in a wireline network. The BNG includes an interworking function in a control plane (IF-CP), the IF-CP configured to use a control plane interface (N1?/N2?) between the BNG in the wireline network and a fifth generation (5G) core in a 5G network to couple a control plane of the BNG to a control plane of the 5G core; an interworking function in a user plane (IF-UP), the IF-UP configured to use a user plane interface (N3?) between the BNG in the wireline network and the 5G core in the 5G network to couple a user plane of the BNG to a user plane of the 5G core; and a transmitter configured to transmit data packets toward the 5G core after the user plane of the BNG and the user plane of the 5G core have been coupled.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: This application provides a network handover method and an apparatus. Before a terminal device is handed over from a first network to a second network, the terminal device sets up a first tunnel to a first interworking device, where a communication identifier, of the terminal device, in the first tunnel is a first identifier the first identifier is an identifier used in the first network by the terminal device, and the first interworking device is an interface device in the first network and oriented toward a network other than the first network. After the terminal device is handed over from the first network to the second network, the terminal device sends an update request to the first interworking device, where the update request to update the communication identifier to a second identifier, and the second identifier is an identifier used in the second network by the terminal device.

Abstract: A prefabricated substrate, a flexible substrate, a flexible module and a fabrication method, and a display device are provided. The prefabricated substrate includes a first film layer as a rigid film layer, and a second film layer as a flexible film layer. The second film layer at least partially wraps the first film layer. The first film layer includes a first surface and a second surface. The second film layer at least includes a first portion located on a side of the first surface away from the second surface, and a second portion and a third portion located on a side of the second surface away from the first surface. The second portion and the third portion are attached on the second surface through a first adhesive layer and a second adhesive layer, respectively. The second portion and the third portion are spaced apart by a gap.

Abstract: A configuration serving network element may configure information about the configuration serving network element for a fifth generation (5G) network architecture. A terminal device may obtain the information about the configuration serving network element from the 5G network architecture. The information about the configuration serving network element includes address information of the configuration serving network element. Therefore, the terminal device can establish a connection to the configuration serving network element based on the address information of the configuration serving network element, so that the configuration serving network element can automatically configure the terminal device by using the 5G network architecture.

Abstract: A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.

Abstract: A broadband network gateway (BNG) in a wireline network. The BNG includes an interworking function in a control plane (IF-CP), the IF-CP configured to use a control plane interface (N1?/N2?) between the BNG in the wireline network and a fifth generation (5G) core in a 5G network to couple a control plane of the BNG to a control plane of the 5G core; an interworking function in a user plane (IF-UP), the IF-UP configured to use a user plane interface (N3?) between the BNG in the wireline network and the 5G core in the 5G network to couple a user plane of the BNG to a user plane of the 5G core; and a transmitter configured to transmit data packets toward the 5G core after the user plane of the BNG and the user plane of the 5G core have been coupled.

Abstract: A data packet verification method and a device improve network security. The method includes: receiving a data packet of a terminal device, where the data packet carries a first token and a service identifier, and the service identifier is used to indicate a type of a service to which the data packet belongs; obtaining first input information based on the data packet, and generating a second token based on the first input information, where the first input information includes an identifier of the terminal device and the service identifier carried in the data packet; and sending the data packet when the first token is the same as the second token.

Abstract: The subject technology requests a group identifier (ID) based on an item identification indicator to an extension application programming interface (API). The subject technology requests, using the extension API, a set of augmented reality (AR) content generator IDs, based on the item identification indicator, to a shopping AR content generator service. The subject technology receives the set of AR content generator IDs based on a mapping of the item identification indicator to a collection of AR content generator IDs. The subject technology requests, using the extension API, first metadata associated with the set of AR content generators and the item identification indicator to the shopping AR content generator service. The subject technology requests, using the extension API, a set of products based on the first metadata. The subject technology generates, using the extension API, a group ID based on the set of products. The subject technology receives the group ID.

Abstract: The present disclosure provides a method for generate array element excitation of a conformal array based on an iterative algorithm, the method comprises obtaining a first index of a pattern of an array antenna by a processor; obtaining multiple optimization objectives according to design indexes of the array antenna by the processor; based on the first index, iteratively determining, by the processor, a first array element excitation satisfying a dynamic range ratio (DRR) of an array element excitation amplitude under the first index through a preset conversion relationship and a preset approach; based on the first array element excitation, obtaining, by the processor, a second array element excitation satisfying the multiple optimization objectives under a constraint of the DRR of the array element excitation amplitude through a solution algorithm; based on the second array element excitation, the design indexes, and basic parameters, generating, by the processor, the array antenna, the basic parameters inc

Abstract: The disclosure provides a power control device, which comprises a bleeder circuit forming a first discharging path and an aux low-voltage (LV) power supply unit forming a second discharging path. The bleeder circuit is connected with a voltage-regulating capacitor stably maintaining the high-voltage (HV) level from a HV battery. The aux LV power supply unit is connected with the bleeder circuit and the voltage-regulating capacitor in parallel. The aux LV power supply unit provides an aux LV level to the driver, when the power system operates abnormally, the HV level is discharged through the first and second discharging path and/or a third discharging path formed by a driver and a motor.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: The present invention discloses Lactobacillus sakei for alleviating allergy and a preparation method thereof, and particularly Lactobacillus sakei for alleviating wheat-dependent, exercise-induced anaphylaxis (WDEIA). The Lactobacillus sakei is classified and named as Lactobacillus sakei. The Lactobacillus sakei has been preserved in China Center for Type Culture Collection since Apr. 12, 2003, with a preservation number of CCTCC DB 20082413. The Lactobacillus sakei can regulate the immune function of a human body to prevent/treat WDEIA by reducing the contents of specific IgE and histamine in serum of WDEIA patients.

Abstract: A scanning antenna is provided in the present disclosure. The scanning antenna includes a first substrate and a second substrate which are arranged oppositely; a liquid crystal layer between the first substrate and the second substrate; and a feed signal access terminal and a plurality of phase shift units, where the plurality of phase shift units is connected with each other, each phase shift unit is connected to the feed signal access terminal, and electrical lengths between at least two phase shift units and the feed signal access terminal are different. The present disclosure not only realizes one-dimensional wave beam scanning, but also has desirable scanning effect. The bias voltage is not needed to be independently applied to each phase shift unit, which can greatly simplify the bias voltage line configuration and be beneficial for reducing production cost and wiring difficulty.

Abstract: The present disclosure provides a coal bump control method for sectional hydraulic fracturing regions of a near vertical ultra thick coal seam. The method includes: deepening a main shaft from a mining level to a fracturing level; excavating a cross-hole from a roof rock layer of a coal seam at the fracturing level to enter a coal seam being mined, and excavating a roadway along the strike of the coal seam; and drilling hydraulic fracturing boreholes in a dedicated fracturing roadway along an inclination angle of the coal seam to the coal seam above the roadway, wherein the length of the borehole makes the borehole in communication with a goaf, and the spacing of the boreholes along the strike and the sectional spacing of the boreholes in an inclination direction are designed according to the parameters of fracturing equipments and the fracturing length.

Abstract: A memory circuit includes a sense amplifier coupled to a non-volatile memory cell, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The sense amplifier includes a comparator. The comparator includes a first input terminal coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage, a second input terminal configured to receive a second voltage, and a first output terminal configured to output a first output signal. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier. The detection circuit includes a first inverter. A first input terminal of the first inverter is configured to receive the first output signal. A first output terminal of the first inverter is configured to generate an inverted first output signal.