Abstract: A level shifter includes a self-initialization circuit. The self-initialization circuit judges whether the input signal and the inverted input signal received by the level shifter are invalid while a power supply voltage is powered up. If the self-initialization circuit confirms that the input signal and the inverted input signal received by the level shifter are invalid, the self-initialization circuit controls the level shifter to be maintained in a self-initializing power up state. Consequently, the output signal from the level shifter has the specified voltage level.

Abstract: A level shifter includes a self-initialization circuit. The self-initialization circuit judges whether the input signal and the inverted input signal received by the level shifter are invalid while a power supply voltage is powered up. If the self-initialization circuit confirms that the input signal and the inverted input signal received by the level shifter are invalid, the self-initialization circuit controls the level shifter to be maintained in a self-initializing power up state. Consequently, the output signal from the level shifter has the specified voltage level.

Abstract: A level shifting circuit generates a pulse signal, when both of the logic levels of two complementary input signals of a level shifter has changed while both of the logic levels of two output signals of the level shifter present at low logic level, to pull up either one of the output signals of the level shifter to a second high logic level. Once the logic level of both output signals at the first output node and the second output node present complementary, the level shifting circuit stops pulling up the output signal.

Abstract: A level shifting circuit generates a pulse signal, when both of the logic levels of two complementary input signals of a level shifter has changed while both of the logic levels of two output signals of the level shifter present at low logic level, to pull up either one of the output signals of the level shifter to a second high logic level. Once the logic level of both output signals at the first output node and the second output node present complementary, the level shifting circuit stops pulling up the output signal.

Abstract: A pulse delay circuit includes a pull down element, a first pull up element, a first delay unit, a second delay unit, a second pull up element, and an inverted buffer. The pull down element is connected to an input pulse signal, a node b and a first voltage. The first pull up element is connected to a node c, a second voltage and the node b. The first delay unit has a reset terminal. The first delay unit is connected to the node b and the node c. The second delay unit is connected to the node c and the node d. The second pull up element is connected to the node d, the second voltage and the node c. The inverted buffer is connected to the node c and the reset terminal. Moreover, a delayed pulse signal is outputted from the inverted buffer.

Abstract: A pulse delay circuit includes a pull down element, a first pull up element, a first delay unit, a second delay unit, a second pull up element, and an inverted buffer. The pull down element is connected to an input pulse signal, a node b and a first voltage. The first pull up element is connected to a node c, a second voltage and the node b. The first delay unit has a reset terminal. The first delay unit is connected to the node b and the node c. The second delay unit is connected to the node c and the node d. The second pull up element is connected to the node d, the second voltage and the node c. The inverted buffer is connected to the node c and the reset terminal. Moreover, a delayed pulse signal is outputted from the inverted buffer.