Abstract: An error detecting system, comprising: a control circuit; and a first error detecting circuit, coupled to the control circuit, configure to detect error of input data. The control circuit controls the first error detecting circuit to use a first setting to detect the error in a first time period, controls the first error detecting circuit to use a second setting to detect the error in a second time period following the first time period, and controls the first error detecting circuit to generate a first detecting result corresponding to the first setting and the second setting after the detection corresponding to the first setting and the second setting are completed.

Abstract: An error detecting system, comprising: a control circuit; and a first error detecting circuit, coupled to the control circuit, configure to detect error of input data. The control circuit controls the first error detecting circuit to use a first setting to detect the error in a first time period, controls the first error detecting circuit to use a second setting to detect the error in a second time period following the first time period, and controls the first error detecting circuit to generate a first detecting result corresponding to the first setting and the second setting after the detection corresponding to the first setting and the second setting are completed.

Abstract: The present invention provides a protection circuit and related operation control method to enable the PFM circuit when the operating duration of the PFM circuit is not greater than a first threshold, and disables the PFM circuit when a rest duration of the PFM circuit is not greater than a second threshold. The present invention further provides a protection circuit and related operation control method to avoid starting excessive vertical scanning operations within one frame scanning period by masking one of the gate scanning start signal STV, the gate clock signal CKV and the gate discharge signal OEV. The present invention further provides a protection circuit and related operation control method to disable the gate scanning start signal STV when the number of clock cycles is not equal to a target number of clock cycles, which protects the gate driver from overload.

Abstract: A method of data dependent pre-charging for a source driver of a liquid crystal display (LCD) is disclosed. Pre-charging is dynamically performed among plural pre-charging schemes according to pixel data corresponding to required output voltage levels to be outputted from channels of the source driver.

Abstract: In a method of dynamic charge sharing for a display device, it is determined whether a current line of a data driver has polarity inverted from a preceding line. Charge sharing is performed globally, if it is determined that the current line is polarity inverted from the preceding line. It is further determined whether the current line and the preceding line are substantially different, if it is determined that the current line is not polarity inverted from the preceding line. Charge sharing is performed in groups if it is determined that the current line and the preceding line are substantially different; otherwise, no charge sharing is performed.

Abstract: A dithering method for an LCD is disclosed and comprises a plurality of steps. First, a plurality of long-bit gray-level signals are received. Each of the long-bit gray-level signal is transformed to a short-bit gray-level signal and at least one LSB is obtained based on the bit length difference between the long-bit gray-level signal and the short-bit gray-level signal. A sequence of frames is generated by the short-bit gray-level signals, and the frames can be classified into different groups according to the LSB. The offset pattern is applied on the frames, wherein the offset pattern is displayed at the same polarity in the same column of each frame in the same group.

Abstract: A dithering method for an LCD is disclosed and comprises a plurality of steps. First, a plurality of long-bit gray-level signals are received. Each of the long-bit gray-level signal is transformed to a short-bit gray-level signal and at least one LSB is obtained based on the bit length difference between the long-bit gray-level signal and the short-bit gray-level signal. A sequence of frames is generated by the short-bit gray-level signals, and the frames can be classified into different groups according to the LSB. The offset pattern is applied on the frames, wherein the offset pattern is displayed at the same polarity in the same column of each frame in the same group.

Abstract: A source driver for driver-on-panel systems. The source driver includes a digital buffer to receive and schedule externally input digital video data, a set of shift registers to generate corresponding sampling control signals according to the data scheduled, a first set of latches to sample the scheduled data according to the sampling control signals and thus generate corresponding digital video data samples, a second set of latches to hold the samples, a set of level shifts to convert the held samples into high-voltage digital signals, a set of digital-to-analog converters to convert the high-voltage digital signals into analog signals, a set of analog buffers to drive the analog signals to a high-loading display panel, and a set of demultiplexers to output the analog signals at different times to appropriate display positions using time division multiplexing (TDM).