Patents by Inventor Huan-Sheng WEI

Huan-Sheng WEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098923
    Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Huan-Sheng WEI, Hung-Li CHIANG, Chia-Wen LIU, Yi-Ming SHEU, Zhiqiang WU, Chung-Cheng WU, Ying-Keung LEUNG
  • Publication number: 20190067121
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Hung-Li CHIANG, I-Sheng CHEN, Tzu-Chiang CHEN, Tung-Ying LEE, Szu-Wei HUANG, Huan-Sheng WEI
  • Publication number: 20180337094
    Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh, Chung-Cheng Wu, Yee-Chia Yeo
  • Publication number: 20180301560
    Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 18, 2018
    Inventors: Huan-Sheng WEI, Hung-Li CHIANG, Chia-Wen LIU, Yi-Ming SHEU, Zhiqiang WU, Chung-Cheng WU, Ying-Keung LEUNG
  • Patent number: 10008603
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Publication number: 20180151438
    Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.
    Type: Application
    Filed: August 2, 2017
    Publication date: May 31, 2018
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh, Chung-Cheng Wu, Yee-Chia Yeo
  • Publication number: 20180145176
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Huan-Sheng WEI, Hung-Li CHIANG, Chia-Wen LIU, Yi-Ming SHEU, Zhiqiang WU, Chung-Cheng WU, Ying-Keung LEUNG