Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.

Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.

Abstract: This invention discloses a system and method for detecting a cover with an abnormal condition. The system includes a transport track for defining a sliding direction of at least one cover with a detection surface. The transport track has a detection area and a cover removal area, and includes a pair of bottom rails and a pair of side rails. The pair of bottom rails support the cover at an inclination angle so that the cover slides on the pair of bottom rails. The cover is located between the pair of side rails, and the sliding direction of the cover is defined by the pair of side rails. The detection area is used for detecting the detection surface of the cover, and the cover removal area has an outlet for removing a cover with an abnormal condition determined based on a detection result of the detection surface thereof.

Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

Abstract: A lid detecting system includes a first lid screwing device, a second lid screwing device, a scanning device and a removing device. The first lid screwing device is configured for positioning a lid of a container on a body of the container and rotationally tightening the lid of the container to the body of the container by a pre-screwing torque. The second lid screwing device is configured for rotationally tightening the lid of the container to the body of the container by a screwing torque. The scanning device is disposed between the first lid screwing device and the second lid screwing device and configured for scanning a top surface of the lid of the container so as to obtain a detecting value. The removing device is configured for removing the container when the detecting value is greater than a predetermined value.

Abstract: This invention discloses a system and method for detecting a cover with an abnormal condition. The system includes a transport track for defining a sliding direction of at least one cover with a detection surface. The transport track has a detection area and a cover removal area, and includes a pair of bottom rails and a pair of side rails. The pair of bottom rails support the cover at an inclination angle so that the cover slides on the pair of bottom rails. The cover is located between the pair of side rails, and the sliding direction of the cover is defined by the pair of side rails. The detection area is used for detecting the detection surface of the cover, and the cover removal area has an outlet for removing a cover with an abnormal condition determined based on a detection result of the detection surface thereof.

Abstract: A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.

Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.

Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.

Abstract: A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.

Abstract: A digital audio/video playback system capable of controlling audio and video playback speed for decoding a digital audio/video signal and then outputting such signal. The system includes: a loader configured to receive the digital audio/video signals, a parser configured to resolve the digital audio/video signals into a video bitstream and an audio bitstream, a video decoder and an audio decoder respectively configured to receive and decode the video bitstream and the audio bitstream, and a playback speed controller configured to adjust the sound frequency of the decoded audio based on a set playback speed and output the decoded video/audio at the set playback speed.

Abstract: The present invention discloses an automatic storage box comprising a bottom case, a receptacle set, a receptacle, a top cover, and a rotary cover set. The inner surface of the bottom case is concaved to form an accommodation basin. A battery bay and a proximity sensor set are respectively arranged at two sides of the accommodation basin, and a dynamic device is arranged therebetween. The receptacle set and the receptacle are respectively detachably installed to the base case. The inner portion of the top cover is concaved downward to form a recess, and the lower rim of the top cover has a positioning element used to engage with the receptacle set. The rotary cover set is arranged above the top cover and pivotally coupled to the receptacle set. When the proximity sensor set detects the approach of a human body, the dynamic device instantly drives the movable cover to rotate to open.

Abstract: An earthquake alarm clock includes a time display device for displaying time with a beeper and a detecting device. The time display device has a guiding member, along which a movable member runs. When an earthquake takes place, the movable member runs along the guiding member and hits the detecting device. The detecting device is electrically connected the beeper to command the beeper broadcasting an alarm when the detecting device is started.

Abstract: A digital audio/video playback system capable of controlling audio and video playback speed for decoding a digital audio/video signal and then outputting such signal. The system includes: a loader configured to receive the digital audio/video signals, a parser configured to resolve the digital audio/video signals into a video bitstream and an audio bitstream, a video decoder and an audio decoder respectively configured to receive and decode the video bitstream and the audio bitstream, and a playback speed controller configured to adjust the sound frequency of the decoded audio based on a set playback speed and output the decoded video/audio at the set playback speed.

Abstract: A tunable ESD device for multi-power application. The ESD device comprises a substrate, at least one first well of a first conductivity, and a doped region of a second conductivity. The first wells of the first conductivity are located in the substrate. The doped region of the second conductivity substantially surrounds the first wells of the first conductivity. The doped region of the second conductivity is a drain region of a MOSFET and the distance thereto from the first wells of the first conductivity is between 0.01 ?m and 1.5 ?m.