Abstract: The present invention is an ADSL encoder and decoder. Wherein, the ADSL encoder comprises a digital signal processor, a buffer, a bit extractor and a constellation point mapper. The digital signal processor delivers data bits to the buffer, and again the delivered data bits are transmitted to the bit extractor by buffer. Bit extractor shifts partial received data bits to an extracted data. The constellation point mapper processes constellation point mapping operation corresponding to the extracted data based on transmitted bits that a sub-carrier can transmit. The ADSL decoder comprises a constellation decoder, a bit packet component and a buffer. The constellation decoder combines a horizontal axis data and a vertical axis data to packed data depending on constellation decoding procedures. The bit packet component stores extracted data to digital data in sequence, and the digital data is stored by buffer in sequence as well, then transmitted to digital signal processor.

Abstract: The present invention is an ADSL encoder and decoder. Wherein, the ADSL encoder comprises a digital signal processor, a buffer, a bit extractor and a constellation point mapper. The digital signal processor delivers data bits to the buffer, and again the delivered data bits are transmitted to the bit extractor by buffer. Bit extractor shifts partial received data bits to an extracted data. The constellation point mapper processes constellation point mapping operation corresponding to the extracted data based on transmitted bits that a sub-carrier can transmit. The ADSL decoder comprises a constellation decoder, a bit packet component and a buffer. The constellation decoder combines a horizontal axis data and a vertical axis data to packed data depending on constellation decoding procedures. The bit packet component stores extracted data to digital data in sequence, and the digital data is stored by buffer in sequence as well, then transmitted to digital signal processor.

Abstract: The present invention is an ADSL encoder and decoder. Wherein, the ADSL encoder comprises a digital signal processor, a buffer, a bit extractor and a constellation point mapper. The digital signal processor delivers data bits to the buffer, and again the delivered data bits are transmitted to the bit extractor by buffer. Bit extractor shifts partial received data bits to an extracted data. The constellation point mapper processes constellation point mapping operation corresponding to the extracted data based on transmitted bits that a sub-carrier can transmit. The ADSL decoder comprises a constellation decoder, a bit packet component and a buffer. The constellation decoder combines a horizontal axis data and a vertical axis data to packed data depending on constellation decoding procedures. The bit packet component stores extracted data to digital data in sequence, and the digital data is stored by buffer in sequence as well, then transmitted to digital signal processor.

Abstract: The present invention discloses a PCI extended function interface and PCI device using such an interface. The PCI extended function interface is suitable for use in a PCI device comprising a master device and at least one slave device. The PCI extended function interface comprises at least one connecting port and a first circuit. The slave device is coupled to a corresponding connecting port and the PCI extended function interface transmits a control signal through the connecting port to control the operation of a corresponding slave device. The first circuit is used to determine the configuration space.

Abstract: A data processing method of fast Fourier transform/inverse Fourier transform (FFT/IFFT) performed by a FFT/IFFT processor for used in a communication system is also disclosed. The FFT/IFFT processor includes a plurality of butterfly addition (BF) stages, the data includes a plurality of points, and each point includes a sign bit, at least one integral bit, and a plurality of decimal bits. The method comprises the steps of determining an overflow may occur in which of the BF stages when performing butterfly addition on the points of the data through detecting a preamble signal; and reserving one of the decimal bits of each point of the data to be an additional integral bit before performing the butterfly addition by the BF stage in which the overflow may occur.

Abstract: The present invention provides sequential feedback Header Error Correction (HEC) checking method and circuit for Asynchronous Transfer Mode (ATM). With design of hardware circuit, the present invention of sequential feedback Header Error Correction (HEC) checking method and circuit will allocate the cell boundary in ATM communication, and meanwhile control the state switching among three operation for cell delineation logic, i.e., HUNT, PRESYNC and SYNC.

Abstract: The present invention is an ADSL encoder and decoder. Wherein, the ADSL encoder comprises a digital signal processor, a buffer, a bit extractor and a constellation point mapper. The digital signal processor delivers data bits to the buffer, and again the delivered data bits are transmitted to the bit extractor by buffer. Bit extractor shifts partial received data bits to an extracted data. The constellation point mapper processes constellation point mapping operation corresponding to the extracted data based on transmitted bits that a sub-carrier can transmit. The ADSL decoder comprises a constellation decoder, a bit packet component and a buffer. The constellation decoder combines a horizontal axis data and a vertical axis data to packed data depending on constellation decoding procedures. The bit packet component stores extracted data to digital data in sequence, and the digital data is stored by buffer in sequence as well, then transmitted to digital signal processor.

Abstract: The present invention discloses a PCI extended function interface and PCI device using such an interface. The PCI extended function interface is suitable for use in a PCI device comprising a master device and at least one slave device. The PCI extended function interface comprises at least one connecting port and a first circuit. The slave device is coupled to a corresponding connecting port and the PCI extended function interface transmits a control signal through the connecting port to control the operation of a corresponding slave device. The first circuit is used to determine the configuration space.