Patents by Inventor HUAN-YU SHIH

HUAN-YU SHIH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11676898
    Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
  • Publication number: 20220367376
    Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
  • Publication number: 20210391275
    Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
  • Patent number: 10269923
    Abstract: In a method of manufacturing a high-electron mobility transistor (HEMT), a first Group III-V semiconductor layer is formed on a substrate. The first Group III-V semiconductor layer is patterned to form a fin and a recessed surface. A second Group III-V semiconductor layer is formed to cover a top surface and all side surfaces of the fin and the recessed surface. The second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Wei-Hao Lee, Huan-yu Shih
  • Publication number: 20180108753
    Abstract: In a method of manufacturing a high-electron mobility transistor (HEMT), a first Group III-V semiconductor layer is formed on a substrate. The first Group III-V semiconductor layer is patterned to form a fin and a recessed surface. A second Group III-V semiconductor layer is formed to cover a top surface and all side surfaces of the fin and the recessed surface. The second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed.
    Type: Application
    Filed: September 13, 2017
    Publication date: April 19, 2018
    Inventors: Miin-Jang Chen, Wei-Hao Lee, Huan-yu Shih
  • Publication number: 20170162378
    Abstract: A method of manufacturing a substrate for epitaxy is disclosed, including the following steps. Dispose a buffer layer on a base, wherein the buffer layer is constituted by stacked nitride layers formed by the process of atomic layer deposition. The buffer layer could alternatively be constituted by stacked at least one first buffer sub-layer and at least one second buffer sub-layer, wherein the first and second buffer sub-layers are respectively constituted by layered first nitride layers and layered second nitride layers, which are both formed by the process of atomic layer deposition. While forming the buffer layer, perform ion bombardment each time a single layer of the nitride layer, the first nitride layer, or the second nitride layer is formed. Whereby, the base and the buffer layer constitute the substrate for epitaxy, which effectively enhances the crystallinity of the buffer layer.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 8, 2017
    Inventors: Miin-Jang CHEN, Yuan-Chuan CHUANG, Huan-Yu SHIH, Ying-Ru SHIH, Wen-Ching HSU
  • Patent number: 9627197
    Abstract: The invention provides a composite substrate, a semiconductor device including such composite substrate, and a method of making the same. In particular, the composite substrate of the invention includes a nitride-based single crystal layer transformed from a nitride-based poly-crystal layer, which has a specific thickness of approximately between 2 nm and 100 nm.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 18, 2017
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Miin-Jang Chen, Huan-Yu Shih, Wen-Ching Hsu, Ray-Ming Lin
  • Publication number: 20150294857
    Abstract: The invention provides a composite substrate, a semiconductor device including such composite substrate, and a method of making the same. In particular, the composite substrate of the invention includes a nitride-based single crystal layer transformed from a nitride-based poly-crystal layer, which has a specific thickness of approximately between 2 nm and 100 nm.
    Type: Application
    Filed: April 15, 2015
    Publication date: October 15, 2015
    Applicants: GLOBALWAFERS CO., LTD.
    Inventors: MIIN-JANG CHEN, HUAN-YU SHIH, WEN-CHING HSU, RAY-MING LIN