Patents by Inventor Huan-Yung Tseng

Huan-Yung Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7464357
    Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: December 9, 2008
    Assignee: Faraday Technology Corp.
    Inventors: An-Ru Andrew Cheng, Chang-Song Lin, Tzu-Chun Liu, Huan-Yung Tseng
  • Patent number: 7299391
    Abstract: A circuit for control and observation of a scan chain. The circuit comprises a group of first scan cells connected in series, receiving a first data signal and outputting a second data signal, a multiplexer receiving the first and second data signal, and selectively outputting the first and second data signal in response to a selection signal, and a group of second scan cells connected in series, receiving the first or second data signal from the multiplexer, and outputting a third data signal.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: November 20, 2007
    Assignee: Faraday Technology Corp.
    Inventor: Huan-Yung Tseng
  • Publication number: 20060123375
    Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.
    Type: Application
    Filed: January 30, 2006
    Publication date: June 8, 2006
    Inventors: An-Ru Cheng, Chang-Song Lin, Tzu-Chun Liu, Huan-Yung Tseng
  • Patent number: 7036099
    Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: April 25, 2006
    Assignee: Faraday Technology Corp.
    Inventors: An-Ru Andrew Cheng, Chang-Song Lin, Tzu-Chun Liu, Huan-Yung Tseng
  • Publication number: 20050022142
    Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.
    Type: Application
    Filed: July 25, 2003
    Publication date: January 27, 2005
    Inventors: An-Ru Andrew Cheng, Chang-Song Lin, Tzu-Chun Liu, Huan-Yung Tseng
  • Publication number: 20040081208
    Abstract: A circuit for control and observation of a scan chain. The circuit comprises a group of first scan cells connected in series, receiving a first data signal and outputting a second data signal, a multiplexer receiving the first and second data signal, and selectively outputting the first and second data signal in response to a selection signal, and a group of second scan cells connected in series, receiving the first or second data signal from the multiplexer, and outputting a third data signal.
    Type: Application
    Filed: October 29, 2002
    Publication date: April 29, 2004
    Inventor: Huan-Yung Tseng