Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.

Abstract: A compound of Formula (I): or a pharmaceutically acceptable salt thereof, in which Ring X is a 3 to 7 membered monocyclic ring, at least one of R1, R2, R3, and R4 is OR5 or CH2OR5 and the other R1, R2, R3, and R4 each independently are halogen, OH, OR5, CH2OR5, CO2H, OC?OR6, (C?O)R6, R6, C1-10 alkyl, C2-10 alkenyl, C2-10 alkynyl, H, or absent. Also provided herein are therapeutic uses of the compound of Formula (I).

Abstract: Methods, systems, and apparatuses include moving a portion of memory to a garbage pool in response to determining that the portion of memory is invalid. The portion of memory is erased in response to determining that the portion of memory is invalid. A request to move an additional portion of memory to a free pool from the garbage pool is received. A free pool includes a queue including erased portions of memory, which serve as next portions of memory to fulfill subsequent cursor requests. The erased portion of memory is moved from the garbage pool to the free pool.

Abstract: An integrated circuit (IC) device includes memory cells each including first through fourth memory elements. The first memory element is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line. The second memory element is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor. The first and second memory elements are arranged in a first row along the first axis. The third memory element is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor electrically coupled to the first conductor. The fourth memory element is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line. The third and fourth memory elements are arranged, along the first axis, in a second row spaced from the first row along an axis transverse to the first axis.

Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Abstract: A catalyst composition for hydrogenating 4,4?-methylenedianiline derivatives is provided. The catalyst composition includes a carrier including aluminum oxide and magnesium oxide, a rhodium-ruthenium active layer loaded on the surface of the carrier, and a solvent including an organic amine. The weight percentage of magnesium oxide in the carrier is between 12% and 30%. A method for preparing 4,4?-methylene bis(cyclohexylamine) derivatives using the catalyst composition is also provided.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and performs a first coarse valley tracking calibration operation on the segment of the memory array. The control logic further configures a read voltage level and one or more parameters associated with the read operation based on a result of the first coarse valley tracking calibration operation and performs a second fine valley tracking calibration operation on the segment of the memory array using the configured read voltage level and the configured one or more parameters.

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

Abstract: A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.

Abstract: Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line.

Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that a temperature associated with the memory device satisfies a threshold criterion; determining a memory access operation type of the memory access operation; and performing the memory access operation on the set of cells associated with the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the memory access operation type and the temperature associated with the memory device.

Abstract: A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.