Patents by Inventor Huang-Chun Wen
Huang-Chun Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230170256Abstract: A method of forming an integrated circuit is described. The method first positions a semiconductor wafer in a processing chamber, and second, laser anneals at least a portion of the semiconductor wafer. The laser annealing includes tracing a first laser beam, in a first path having a first direction, across the at least a portion of the semiconductor wafer, tracing a second laser beam, in a second path having a second direction, opposite to and colinear with the first direction, across the at least a portion of the semiconductor wafer.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Xiangzheng Bo, Huang-Chun Wen
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Patent number: 11495607Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.Type: GrantFiled: August 7, 2018Date of Patent: November 8, 2022Assignee: Texas Instruments IncorporatedInventors: Huang-Chun Wen, Richard Allen Bailey, Antonio Guillermo Acosta, John A. Rodriguez, Scott Robert Summerfelt, Kemal Tamer San
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Publication number: 20180374861Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.Type: ApplicationFiled: August 7, 2018Publication date: December 27, 2018Inventors: Huang-Chun Wen, Richard Allen Bailey, Antonio Guillemo Acosta, John A. Rodriguez, Scott Robert Summerfelt, Kemal Tamer San
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Publication number: 20160086960Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.Type: ApplicationFiled: June 2, 2015Publication date: March 24, 2016Inventors: Huang-Chun Wen, Richard Allen Bailey, Antonio Guillermo Acosta, John A. Rodriguez, Scott Robert Summerfelt, Kemal Tamer San
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Patent number: 9070575Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.Type: GrantFiled: July 29, 2013Date of Patent: June 30, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
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Patent number: 8753952Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.Type: GrantFiled: December 20, 2011Date of Patent: June 17, 2014Assignee: Texas Instruments IncorporatedInventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
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Publication number: 20130313679Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.Type: ApplicationFiled: July 29, 2013Publication date: November 28, 2013Inventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
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Patent number: 8482080Abstract: A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.Type: GrantFiled: May 18, 2012Date of Patent: July 9, 2013Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Huang-Chun Wen
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Publication number: 20130062733Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.Type: ApplicationFiled: December 20, 2011Publication date: March 14, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
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Publication number: 20120228715Abstract: A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Hiroaki NIIMI, Huang-Chun WEN
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Patent number: 8202773Abstract: A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.Type: GrantFiled: August 31, 2009Date of Patent: June 19, 2012Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Huang-Chun Wen
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Publication number: 20100052071Abstract: A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.Type: ApplicationFiled: August 31, 2009Publication date: March 4, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Hiroaki NIIMI, Huang-Chun WEN
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Publication number: 20090039441Abstract: Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a current source, a second doped region configured to drain current from the first doped region when an electric field is modified between the first doped region and the second doped region, and a gate electrode configured to modify the electric field. The gate electrode may include a high-k layer, a hafnium-based metal layer formed above the high-k layer, and a polysilicon layer formed above the hafnium-based metal layer. In a further embodiment, the gate electrode further comprises a titanium-based metal layer formed between the hafnium-based metal layer and the polysilicon layer.Type: ApplicationFiled: August 10, 2007Publication date: February 12, 2009Inventors: Hongfa Luna, Kisik Choi, Prashant Majhi, Husam Alshareef, Huang-Chun Wen, Rusty Harris, Byoung Hun Lee
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Publication number: 20040147070Abstract: The present invention provides a new ultra-shallow junction formation method for nano-MOS technology applications by using conventional ion implantation and rapid thermal annealing techniques without requirement of low energy implant equipments to fabricate ultra-shallow junctions. Diffusion from implanted amorphous silicon (DIA) is performed by junction implant through an amorphous capping layer; the amorphous layer thus acts as a surface solid diffusion source during annealing. A thin oxide is deposited to serve as etching stop layer beneath the amorphous layer. This bilayer amorphous-oxide structure enables easy removal of the amorphous layer and provides good process control and device reliability. By using amorphous silicon layer as the diffusion source for junction formation, implant defects are reduced. Defect-free ultra-shallow junctions can be formed.Type: ApplicationFiled: January 24, 2003Publication date: July 29, 2004Applicant: NATIONAL CHIAO-TUNG UNIVERSITYInventors: Tan Fu Lei, Tzu Yun Chang, Huang-Chun Wen