Abstract: A clock frequency multiplier is provided. The clock frequency multiplier comprises a tracking circuit, a pulsing circuit, and a shaping circuit. The tracking circuit receives a clearing signal and a reference clock signal, outputs the quotient of the number of cycles of the reference clock signal in a cycle of the clearing signal divided by a first predetermined value. The pulsing circuit outputs a pulsing signal wherein the frequency of the pulsing signal is the frequency of the clearing signal multiplied by the first predetermined value. The shaping circuit divides the frequency of the pulsing signal by a second predetermined value and shapes the pulsing signal into a clock signal with a predetermined duty cycle, and outputs the divided and shaped pulsing signal as an output clock signal.

Abstract: The invention provides an apparatus and a method for protecting data. This apparatus includes a sequential-key comparator and a scrambling device, and a storage device stores encrypted data. When a received address signal is not consistent to a key pattern in the sequential-key comparator, the scrambling device rearranges the address signal and generates a scrambled address signal so that the pirated data are the encrypted data corresponding to the scrambled address signal. As the pirated data become useless, the invention enhances the difficulty of pirating the data, thereby ensuring the data security.

Abstract: A clock frequency multiplier is provided. The clock frequency multiplier comprises a tracking circuit, a pulsing circuit, and a shaping circuit. The tracking circuit receives a clearing signal and a reference clock signal, outputs the quotient of the number of cycles of the reference clock signal in a cycle of the clearing signal divided by a first predetermined value. The pulsing circuit outputs a pulsing signal wherein the frequency of the pulsing signal is the frequency of the clearing signal multiplied by the first predetermined value. The shaping circuit divides the frequency of the pulsing signal by a second predetermined value and shapes the pulsing signal into a clock signal with a predetermined duty cycle, and outputs the divided and shaped pulsing signal as an output clock signal.