Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.

Abstract: Example communication methods and apparatus are described. In one example method, a terminal device obtains and sends first information, where the first information indicates non-differential information of at least one first target point at a first moment. The terminal device obtains second information and sends the second information, where the second information indicates differential information of at least one second target point, and each of the at least one second target point corresponds to a first target point in the at least one first target point. Differential information of each of the at least one second target point is determined based on non-differential information of the second target point at a second moment and non-differential information of a corresponding first target point at the first moment, and each of the at least one second target point is a target point sensed by the terminal device at the second moment.

Abstract: An object position determining system comprising: at least one light source, configured to emit light; at least one optical sensor, configured to sense optical data generated based on reflected light of the light; and a processing circuit, configured to compute distance information between the optical sensor and an object which generates the reflected light. The processing circuit further determines a position of the object according to the distance information.

Abstract: The present disclosure relates to pulse shaping-based reference signals. Signaling indicating information that is associated with pulse shaping and information associated with a target length of a sequence for a reference signal such as a demodulation reference signal (DMRS) is communicated between a first communication device and a second communication device in a wireless communication network. The reference signal is also communicated in the wireless communication network. The reference signal comprises a sequence of the target length to which the pulse shaping has been applied. The sequence comprises a base sequence that is determined based on the pulse shaping.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: This application provides a symbol processing method and apparatus. The method includes: A transmitting end generates a first transmit symbol and a second transmit symbol. A length of a cyclic prefix of the first transmit symbol is greater than a length of a cyclic prefix that corresponds to a subcarrier spacing of the first transmit symbol. The transmitting end sends the first transmit symbol and the second transmit symbol. The first transmit symbol and the second transmit symbol are consecutive in time domain. The first transmit symbol is located after the second transmit symbol. The first transmit symbol is a symbol that carries a reference signal, and the second transmit symbol is a symbol that carries a data signal.

Abstract: There is provided an image sensor employing an avalanche diode. The image sensor includes a plurality of pixel circuits arranged in a matrix, a plurality of pulling circuits, a plurality of output circuits and a global current source circuit. Each of the plurality of pixel circuits includes a single photon avalanche diode and a P-type or N-type select switch transistor. Each of the plurality of pulling circuits is arranged corresponding to one pixel circuit column. The global current source circuit is used to form a current mirror with each of the plurality of pulling circuits. Each of the plurality of output circuits is shared by at least two pixel circuits.

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: Embodiments of this application disclose a backscatter communication method and a related apparatus. The method includes: An excitation device determines a first sequence, generates a first signal, and sends the first signal, where the first signal carries the first sequence; after receiving the first signal, a backscatter device modulates backscatter device data onto the received first signal to obtain a second signal, and backscatters the second signal, to implement first scrambling on the backscatter device data by using the first sequence; and a receiving device determines the first sequence, receives the second signal from the backscatter device, and demodulates the received second signal based on the first sequence, to obtain the backscatter device data carried on the second signal.

Abstract: This application provides an example paging indication information transmission method and an example communications apparatus. The method includes the terminal device receiving paging indication information, where the paging indication information includes at least one of the following bits: all or some bits of valid bits of a short message field in downlink control information (DCI), all or some bits of remaining bits of the short message field in the DCI, and all or some bits of a reserved field in the DCI. The method also includes the terminal device determining, based on the paging indication information, whether to detect a physical downlink shared channel (PDSCH).

Abstract: A MRAM device includes a substrate, a first bottom electrode, a first MTJ stack, a first spacer, a topography-smoothing layer and a second ILD layer. The substrate includes a first ILD layer having a metal line. The first MTJ stack is over the first bottom electrode. The first spacer surrounds sidewalls of the first MTJ stack. The topography-smoothing layer extends over a top surface of the first ILD layer, along sidewalls of the first bottom electrode the first spacer. The topography-smoothing layer has a top portion over the first MTJ stack and a first side portion laterally surrounding the first spacer. The first side portion has a maximal lateral thickness greater than a maximal vertical thickness of the top portion. The second ILD layer is over the topography-smoothing layer and has a material different from a material of the topography-smoothing layer.

Abstract: Embodiments include a method and device resulting from the method, including using a radical oxidation process to oxidize a spacer layer which lines the opening after removing a dummy gate electrode. The oxidized layer is removed by an etching process. An STI region disposed below the dummy gate electrode may be partially etched.

Abstract: A stick-shaped paper container according to the present invention is introduced herein, and comprises a covering body, a base seat and a sleeving unit, the respective entire structure of all which is integrally compression-molded with only rendering positive draft angles, respectively, only by a wet-fiber pulp-molding process applied for wet plant-fibrous pulps, thereby being capable of simplifying its mold assembly and lowering its mold cost. The covering body, the sleeving unit and the base seat are assembled together into the entire stick-shaped paper container having a container height-to-width ratio between 2˜5.5.

Abstract: The present invention discloses a carrier used for preparing beverage and a method for fabrication thereof.

Abstract: A terminal device first authenticates whether the terminal device has permission to sense a to-be-measured object. If the terminal device has sensing permission, the terminal device senses the to-be-measured object. If the terminal device has no sensing permission, the terminal device does not sense the to-be-measured object. In this way, privacy leakage of the to-be-measured object is prevented.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

Abstract: The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes an inter-level dielectric (ILD) laterally surrounding a memory device. One or more sidewall spacers are arranged along opposing sides of the memory device. The one or more sidewall spacers have a bottom surface over a bottom of the memory device. An etch stop layer is disposed on the one or more sidewall spacers and along the opposing sides of the memory device. An upper interconnect is arranged directly over the memory device, a top surface of the one or more sidewall spacers, and an upper surface of the etch stop layer.