Patents by Inventor Huang Huang

Huang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11976422
    Abstract: A pulp-molding process and an in-line intelligently drying apparatus therefor, comprise: implementing intelligent-circulation desiccating step and intelligently-wetting step in sequence, between pulp-dredging and forming step and thermo-compression forming step. Intelligent-circulation desiccating step comprises: in accordance to structure and/or outer contour of pulp-molding article, implementing combination of both infrared irradiation step and hot-wind blowing step, thereby self-adaptive eliminating different moistures contained within different portions of initially-compressed semi-finished product, to form evenly-dried semi-finished product. Intelligently-wetting step comprises: in accordance to structure and/or outer contour of pulp-molding article, spray-sprinkling predetermined different adaptive amount of water over different local location within dried semi-finished product, thereby forming wetted semi-finished product having averaged moisture content.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: May 7, 2024
    Assignee: GOLDEN ARROW PRINTING TECHNOLOGY (KUNSHAN) CO., LTD.
    Inventors: Chien-Kuan Kuo, Chun-Huang Huang
  • Patent number: 11977205
    Abstract: An optical element including an optically transparent lens which defines a curved surface having a steepness given by an R/# of from about 0.5 to about 1.0. A film is positioned on the curved surface. The film includes an index layer. A composite layer is positioned on the curved surface having a refractive index greater than the index layer. The composite layer includes HfO2 and Al2O3. The composite layer has a mole fraction X of HfO2, wherein X is from about 0.05 to about 0.95 and a mole fraction of Al2O3 in the composite layer is 1?X.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: May 7, 2024
    Assignee: Corning Incorporated
    Inventors: Ming-Huang Huang, Chang-gyu Kim, Hoon Kim, Soo Ho Park, Jue Wang
  • Publication number: 20240147734
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a memory cell overlying a substrate and comprising a top electrode. A sidewall spacer structure is disposed along sidewalls of the memory cell. The sidewall spacer structure comprises a first spacer layer on the memory cell, a second spacer layer around the first spacer layer, and a third spacer layer around the second spacer layer. The second spacer layer comprises a lateral segment adjacent to a vertical segment. The lateral segment abuts the top electrode and has a top surface aligned with or disposed below a top surface of the top electrode. A first conductive structure overlies the memory cell and contacts the lateral segment and the top electrode.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
  • Publication number: 20240137795
    Abstract: This application relates to the field of communications technologies. A method includes: A first device receives first configuration information sent by a second device. The first configuration information includes at least one of information about a reference signal, frequency range information of a radio frequency signal, or bandwidth range information. The first device measures a first reference signal set, to obtain a first measured value. The first reference signal set includes at least two reference signals. The first device determines an expansion factor ? based on the first configuration information. The first device determines a second measured value based on the first measured value and the expansion factor ?.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 25, 2024
    Inventors: Mao Yan, Huang Huang, Hua Shao, Lei Chen
  • Patent number: 11968047
    Abstract: This application provides a method and an apparatus for sending feedback information and a method and an apparatus for receiving feedback information, to reduce resource waste in a data retransmission process.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: April 23, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Huang Huang, Kuandong Gao, Peng Guan, Bo Fan, Lei Chen
  • Publication number: 20240128126
    Abstract: A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.
    Type: Application
    Filed: November 20, 2023
    Publication date: April 18, 2024
    Inventors: Shu-Uei Jang, Chen-Huang Huang, Ryan Chia-Jen Chen, Shiang-Bau Wang, Shu-Yuan Ku
  • Patent number: 11961919
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Chang, Hsiu-Hao Tsao, Ming-Jhe Sie, Shun-Hui Yang, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
  • Publication number: 20240121068
    Abstract: A communication method and apparatus. A plurality of signals included in a first sequence to M subcarrier blocks used to transmit a reference signal are mapped, where an mth subcarrier block includes Qm subcarriers, and a plurality of signals mapped to a plurality of consecutive subcarriers at a rear location in the mth subcarrier block are the same as a plurality of signals mapped to a plurality of consecutive subcarriers at a front location in a (mod(m, M)+1)th subcarrier block. Signals transmitted on a plurality of reference signal subcarrier blocks are jointly designed, and a cyclic redundancy characteristic is formed in the plurality of reference signal (for example, PTRS) subcarrier blocks.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 11, 2024
    Inventors: Huang HUANG, Qianli MA
  • Patent number: 11952659
    Abstract: Atomic layer deposition methods for coating an optical substrate with magnesium fluoride. The methods include two primary processes. The first process includes the formation of a magnesium oxide layer over a surface of a substrate. The second process includes converting the magnesium oxide layer to a magnesium fluoride layer. These two primary processes may be repeated a plurality of times to create multiple magnesium fluoride layers that make up a magnesium fluoride film. The magnesium fluoride film may serve as an antireflective coating layer for an optical substrate, such as an optical lens.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: April 9, 2024
    Assignee: Corning Incorporated
    Inventors: Ming-Huang Huang, Hoon Kim, Jue Wang
  • Publication number: 20240109230
    Abstract: A manufacturing method of housing structure of electronic device is provided. The manufacturing method includes stacking a first structural layer, a painting layer, and a second structural layer, wherein the painting layer is located between the first and the second structural layers. The layer stacked after the painting layer washes and squeezes at least a portion of the flowing painting layer to form a random texture pattern.
    Type: Application
    Filed: May 16, 2023
    Publication date: April 4, 2024
    Applicants: Acer Incorporated, Nan Pao New Materials (Huaian) Co., Ltd.
    Inventors: Pin-Chueh Lin, Wen-Chieh Tai, Cheng-Nan Ling, Chang-Huang Huang
  • Publication number: 20240113836
    Abstract: A method includes a transmitting end sending a first signal that includes a data signal and a reference signal. A first imaginary reference signal in the reference signal is located at a real signal location of the first signal, and/or a first real reference signal in the reference signal is located at an imaginary signal location of the first signal; and the reference signal is used for phase noise estimation.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Inventors: Huang Huang, Kuandong Gao, Qianli Ma
  • Publication number: 20240106616
    Abstract: A multi-user communication method includes obtaining first information indicating channel information of a first channel on a first frequency domain resource and second information indicating channel information of a second channel on the first frequency domain resource. The method also includes determining phase precoding information based on the first information and the second information. The first channel and the second channel overlap with each other on the first frequency domain resource. Phases of signals transmitted on symmetric subcarriers of the first channel are opposite. Phases of signals transmitted on symmetric subcarriers of the second channel are opposite. After precoding is performed based on the phase precoding information, channel correlation between an equivalent channel of the second channel and an equivalent channel of the first channel is less than channel correlation between the second channel and the first channel.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 28, 2024
    Inventors: Qianli MA, Huang HUANG, Nuwan Suresh FERDINAND
  • Patent number: 11943086
    Abstract: This application provides a symbol processing method and apparatus. The method includes: obtaining a plurality of complex-valued symbols; dividing the plurality of complex-valued symbols into a plurality of sets, where each set corresponds to one transmitted symbol; and performing a copy operation on the plurality of sets, so that two sets corresponding to two transmitted symbols that are consecutive in time domain have some same complex-valued symbols. By enabling two sets corresponding to two transmitted symbols that are consecutive in time domain to have some same complex-valued symbols, a guard interval between symbols can be flexibly configured when a cyclic prefix length is fixed.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 26, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Fengwei Liu, Huang Huang
  • Patent number: 11943084
    Abstract: A method includes generating a data signal based on data, scrambling the data signal with a pseudo-random signal thereby generating a scrambled data signal, generating an amplitude shift keying (ASK) signal based on the scrambled data signal, and transmitting, by a transceiver, the ASK signal.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: March 26, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Kuandong Gao, Mao Yan, Huang Huang
  • Publication number: 20240090340
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Publication number: 20240076105
    Abstract: A sunken-type cup lid, for covering on a cup mouth of a cup body, according to the present invention is disclosed herein, and comprises: a covering panel, a leaning-on portion and a camber-holding portion. On the covering panel, a sunken-type dome structure is formed to expand a contacting area, from the leaning-on portion laterally and tightly fitting against inside the cup body, to the camber-holding portion downwardly and tightly fitting overneath the cup mouth, so as to be in a multi-directional tight fit manner between the cup lid and the cup body. Thus, it can decrease a liquid-leakage probability incurred between the cup lid and the cup body, and an accidentally detaching probability of the cup lid away from the cup body.
    Type: Application
    Filed: July 2, 2023
    Publication date: March 7, 2024
    Inventors: CHIEN-KUAN KUO, CHUN-HUANG HUANG
  • Publication number: 20240073079
    Abstract: Aspects of the present application provide methods and devices for a phase tracking reference (PT-RS) scheme for use by a single carrier Offset QAM (SC-OQAM) transmitter and receiver to estimate, and correct, phase errors that occur over the communication link between the SC-OQAM transmitter and receiver. A transmitter may set the sign (positive or negative) of PT-RS symbols dynamically allowing the transmitter to better utilize IQ interference caused by data symbols and other PT-RS symbols. Another aspect of the present disclosure provides a receiver that can estimate phase error due to phase noise without knowing the sign of PT-RS symbol or the sign of IQ interference. This type of phase error estimation improves the phase noise estimation performance, and thus may improve the overall block error rate (BLER) performance at the receiver.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 29, 2024
    Inventors: NUWAN SURESH FERDINAND, HUANG HUANG, QIANLI MA
  • Publication number: 20240073076
    Abstract: Embodiments of this application provide a communication method and apparatus. In the method, the first communication apparatus may receive a first message, where the first message includes information about an expansion factor. The first communication apparatus determines a quantity of information bits based on the expansion factor, generates a to-be-sent signal based on the quantity of information bits; and transmits the to-be-sent signal. During communication, the communication apparatus uses the expansion factor in transmission, so that the quantity of information bits transmitted in a filter can be increased, to ensure high spectrum utilization and high data transmission efficiency.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qianli MA, Huang HUANG, Kuandong GAO
  • Publication number: 20240072156
    Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate, semiconductor channel sheets disposed over the semiconductor substrate, and source and drain regions located beside the semiconductor channel sheets. A gate structure is disposed between the source and drain regions and disposed over the semiconductor channel sheets. The gate structure laterally surrounds the semiconductor channel sheets. The gate structure includes a top gate electrode structure disposed above the semiconductor channel sheets, and lower gate electrode structures disposed between the semiconductor channel sheets. Sidewall spacers are disposed between the gate structure and source and drain regions, and the sidewall spacers located next to the top gate electrode structure have slant sidewalls.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen, Hsuan-Chih Wu
  • Publication number: 20240069303
    Abstract: An optical focus adjustment module includes an operating ring; a first lens barrel disposed in the operating ring and including three grooves; a second lens barrel disposed in the first lens barrel and including one first protrusion portion and two second protrusion portions, wherein the first protrusion portion and the two second protrusion portions are disposed in the three grooves respectively and adapted to move parallel to a central axis; first and second optical lens assemblies disposed in the first and second lens barrels respectively; a gear disposed in the operating ring and meshed with an inner surface of the operating ring; and a screw rod disposed in a through hole of the first protrusion portion and rotationally synchronized with the gear and the operating ring, whereby the operating ring drives the second lens barrel, and then moves the second optical lens assembly to a predetermined position.
    Type: Application
    Filed: November 7, 2022
    Publication date: February 29, 2024
    Inventor: Ming-Huang HUANG