Patents by Inventor Huang HUANZHANG

Huang HUANZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated bus interface fall and rise time accelerator method
    Patent number: 11711079
    Abstract: An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: July 25, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Michael John Shay, Jonathan Lee Valdez, Kyle Edward Addington, Padmakumar Menon Nambiyath, Huang Huanzhang
  • INTEGRATED BUS INTERFACE FALL AND RISE TIME ACCELERATOR METHOD
    Publication number: 20220278684
    Abstract: An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.
    Type: Application
    Filed: October 20, 2021
    Publication date: September 1, 2022
    Inventors: Michael John SHAY, Jonathan Lee VALDEZ, Kyle Edward ADDINGTON, Padmakumar Menon NAMBIYATH, Huang HUANZHANG