Patents by Inventor Huang-Jen Hsu

Huang-Jen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255150
    Abstract: The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huang-Jen Hsu, Jheng-Si Su, Kung-Ming Liu, Tzuyi Hsieh, Feng-Inn Wu
  • Publication number: 20240387398
    Abstract: The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Huang-Jen HSU, Jheng-Si SU, Kun-Ming LIU, Tzi-Yi SHIEH, Feng-Inn WU
  • Publication number: 20220102285
    Abstract: The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.
    Type: Application
    Filed: July 7, 2021
    Publication date: March 31, 2022
    Inventors: Huang-Jen HSU, Jheng-Si SU, Kun-Ming LIU, Tzi-Yi SHIEH, Feng-Inn WU
  • Patent number: 8992287
    Abstract: The present disclosure relates to a slurry distribution system having a distribution tube connected between a mixing tank and a CMP tool. The mixing tank is configured to generate a polishing mixture comprising a diluted slurry having abrasive particles that enable mechanical polishing of a workpiece. The polishing mixture is transported between the mixing tank and a CMP tool by way of a transport piping. An energy source, in communication with the transport piping, transfers energy to the abrasive particles within the polishing mixture, thereby preventing accumulation of the abrasive particles within the transport piping.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chen Wang, Feng-Inn Wu, Chih-Hung Tsai, Huang-Jen Hsu, Te-Chia Hsu