Patents by Inventor Huang K. Boddu

Huang K. Boddu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CLOCK DIFFERENTIAL BUFFERING
    Publication number: 20150188548
    Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal.
    Type: Application
    Filed: October 13, 2014
    Publication date: July 2, 2015
    Inventors: Choupin Huang, Huang K. Boddu, Stefan Rusu, Nicholas B. Peterson