Abstract: A resistive memory cell includes a lower electrode, a resistive transition metal oxide layer, and an upper electrode. The lower electrode includes at least one lower metallic barrier layer, a lower metal layer including a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer including an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer includes a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer. The upper electrode includes an upper metal layer including a second metal having a melting point higher than 2,000 degrees Celsius and at least one upper metallic barrier layer.

Abstract: The present invention provides a method for writing test parameters into board memory, comprising: establishing a channel-pin mapping table associated with each test board, the channel-pin mapping table indicating that an i-th channel among M channels corresponds to a j-th pin among N pins of the respective test board; converting each test code transmitted by the M channels at a first time into a corresponding set of test parameters; maintaining a channel-code mapping table in a test register, the channel-code mapping table storing the set of test parameters corresponding to the i-th channel among the M channels at the first time; and writing the set of test parameters corresponding to the i-th channel at the first time into a physical address of the board memory of each corresponding test board based on the channel-pin mapping table and the stored channel-code mapping table.

Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. The control logic identify a subset of memory blocks of one or more memory planes that pass a program count operation associated with a last programming level of the set of programming levels. The control logic further terminates execution of the programming operation on the one or more memory planes associated with the subset of memory blocks.

Abstract: A memory device includes a memory array includes memory cells grouped into one or more address ranges. Control logic is coupled to the memory array and configured to detect one or more errors associated with one or more stored data items corresponding to a first address range of one or more address ranges. The control logic can determine that a number of the one or more stored data items exceeds a number of redundant memory locations for the first address space. Control logic can remap an association of a first memory address of at least one of the stored data items from a first address within the first address space to a second address in a second address range, where the second address range includes one or more available redundant memory locations.

Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.

Abstract: A resistive memory cell includes a lower electrode, a resistive transition metal oxide layer, and an upper electrode. The lower electrode includes at least one lower metallic barrier layer, a lower metal layer including a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer including an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer includes a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer. The upper electrode includes an upper metal layer including a second metal having a melting point higher than 2,000 degrees Celsius and at least one upper metallic barrier layer.

Abstract: Control logic in a memory device identifies a segment of the plurality of segments of a memory array of a memory device, and determines a health status for the segment from a plurality of possible health statuses, the plurality of possible health statuses comprising three or more health statuses. The control logic further provides the health status for the segment to a memory sub-system controller associated with the memory device, wherein the memory sub-system controller is to perform a corresponding action with respect to the segment based on the health status, and wherein the corresponding action is different for each of the plurality of possible health statuses.

Abstract: An automatically generating method for generating a simulation circuit includes performing a circuit dividing step, a circuit segmenting step, a main element model generating step, a circuit segment model generating step and a model combining step. The circuit dividing step includes accessing a radio frequency circuit information from a memory unit, and dividing the radio frequency circuit information into a plurality of circuit units. The circuit segmenting step includes transforming each of the circuit units into a plurality of circuit segments. The main element model generating step includes generating at least one main element model. The circuit segment model generating step includes generating a circuit segment model. The circuit segment model is corresponding to each of the circuit segments. The model combining step includes combining the at least one main element model and the circuit segment model corresponding to each of the circuit segments to generate the simulation circuit.

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Abstract: An expansion card holder assembly that accepts different size expansion cards is disclosed. The expansion card holder assembly includes a metal base with grooves that roller features of a metal slide bracket fit into. The metal slide bracket is positioned along the metal base for different size expansion cards. The metal slide bracket is connected with a metal cover that is opened to accept expansions cards. A connector is provided for the expansion card to connect with printed circuit board.

Abstract: A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.

Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

Abstract: An assembly line includes a conveyor belt and an energy charging system. The energy charging system includes (i) a resonator having a TX resonator disposed along the conveyor belt and a RX resonator mounted on and transported by the conveyor belt, (ii) an impedance matching network in communication with the resonator, (iii) and an energy storage device in communication with at least one of the resonator and the impedance matching network. Vmin is a minimum voltage of the energy storage device, and Vcap is a voltage across the energy storage device measured in real time. Energy is transferred from the TX resonator to the RX resonator when the Vcap is less than Vmin of the energy storage device.

Abstract: An expansion card holder assembly that accepts different size expansion cards is disclosed. The expansion card holder assembly includes a metal base with grooves that roller features of a metal slide bracket fit into. The metal slide bracket is positioned along the metal base for different size expansion cards. The metal slide bracket is connected with a metal cover that is opened to accept expansions cards. A connector is provided for the expansion card to connect with printed circuit board.

Abstract: A resistive memory cell includes a lower electrode, a resistive transition metal oxide layer, and an upper electrode. The lower electrode includes at least one lower metallic barrier layer, a lower metal layer including a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer including an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer includes a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer. The upper electrode includes an upper metal layer including a second metal having a melting point higher than 2,000 degrees Celsius and at least one upper metallic barrier layer.

Abstract: A fly ash treatment method includes: a setting step: finding out an initial viscosity value of initial fly ash; a pickling operation step: adding the initial fly ash, water and an acid to a pickling tank, uniformly stirring the mixture, and detecting and adjusting a ratio of components of slurry in the pickling tank to conform to a variation of the curve in the heavy metal leaching test curve graph; a first quantitative output step: inputting the slurry into a first buffer tank and quantitatively output the slurry; a first filtration step: filtering fine particles in the slurry output by from the first buffer tank; a drying and pulverizing step: removing water from the slurry passing through the first filter, and performing pulverizing to form powder; and a rotary kiln cracking step: cracking organic matters in the powder by a rotary kiln, and collecting fly ash cinder.

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).