Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: An interface conversion device is provided to connect a peripheral device and a serial peripheral interface (SPI) of the CPU by using a complex programmable logic device. The peripheral device transmits data to the complex programmable logic device. The complex programmable logic device receives the data by using a universal asynchronous receiver transmitter (UART), converts the data into the data that can be accepted by a serial peripheral interface by using an interface conversion unit, and then transmits the data to a central processing unit (CPU). The CPU transmits the data to the complex programmable logic device, and the complex programmable logic device also converts the data into the data that can be accepted by the universal asynchronous receiver transmitter by using the interface conversion unit, and then transmits the data to the peripheral device.