Patents by Inventor HUANG-LIN CHAO

HUANG-LIN CHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367624
    Abstract: Some implementations described herein provide a method. The method includes forming a channel structure of a transistor. The method includes forming a work function metal (WFM), that includes aluminum and carbon, around the channel structure. Forming the WFM around the channel structure includes applying a chemical soak, with a material of the chemical soak including an aluminum, carbon, and hydrogen based material. The WFM includes a concentration of titanium that is in a range of 0% to less than 1.5% of the WFM. Some implementations described herein provide a transistor. The transistor includes a channel structure and an aluminum carbide (AlC)-based work function material (WFM) disposed around the channel structure. The WFM comprises a concentration of titanium that is in a range of 0% to less than 1.5% of the WFM.
    Type: Application
    Filed: December 29, 2021
    Publication date: November 17, 2022
    Inventors: Hsin-Yi LEE, Huang-Lin CHAO, Chi On CHUI
  • Publication number: 20220359698
    Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Peng-Soon Lim, Ziwei Fang, Huang-Lin Chao
  • Patent number: 11495471
    Abstract: A semiconductor substrate has an exposed surface having a compositionally uniform metal, and an embedded surface having the metal and an oxide. The exposed surface is polished using a first slurry including a first abrasive and a first amine-based alkaline until the embedded surface is exposed. The embedded surface is polished using a second slurry including a second abrasive and a second amine-based alkaline. The second abrasive is different from the first abrasive. The second amine-based alkaline is different from the first amine-based alkaline. The metal and the oxide each has a first and a second removal rate in the first slurry, respectively, and a third and fourth removal rate in the second slurry, respectively. A ratio of the first removal rate to the second removal rate is greater than 30:1, and a ratio of the third removal rate to the fourth removal rate is about 1:0.5 to about 1:2.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 8, 2022
    Inventors: An-Hsuan Lee, Chun-Hung Liao, Chen-Hao Wu, Shen-Nan Lee, Teng-Chun Tsai, Huang-Lin Chao
  • Patent number: 11489056
    Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Peng-Soon Lim, Ziwei Fang, Huang-Lin Chao
  • Publication number: 20220319932
    Abstract: A method of forming a transistor is disclosed. The method includes forming a high-k dielectric constant layer on a semiconductor substrate, forming a pretreatment layer (PL) on the high-k dielectric constant layer, determining a thickness for a conductive work function layer (WFL) based on a target effective work function of the transistor, and forming the conductive work function layer (WFL) on the first pretreatment layer, where the conductive work function layer has a WFL thickness substantially equal to the determined thickness. Forming the transistor also includes forming a coating layer on the first conductive work function layer. The gate stack has a tuned effective work function according to the determined thickness.
    Type: Application
    Filed: January 4, 2022
    Publication date: October 6, 2022
    Inventors: Peng-Soon Lim, Huang-Lin Chao
  • Publication number: 20220310457
    Abstract: A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.
    Type: Application
    Filed: November 23, 2021
    Publication date: September 29, 2022
    Inventors: Huiching Chang, I-Ming Chang, Huang-Lin Chao
  • Publication number: 20220310638
    Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.
    Type: Application
    Filed: September 10, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.
    Inventors: Chung-Liang CHENG, Huang-Lin CHAO
  • Publication number: 20220254927
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed within the gate capping structure and a first via structure disposed on the first contact structure.
    Type: Application
    Filed: September 9, 2021
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manfacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Sheng-Tsung Wang, Huang-Lin Chao
  • Publication number: 20220254684
    Abstract: A semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. The method includes forming first and second source/drain (S/D) regions on first and second fin structures, forming a first dielectric layer between the first and second S/D regions, forming first and second gate-all-around (GAA) structures on the first and second fin structures, forming a second dielectric layer on the first and second GAA structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second GAA structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.
    Type: Application
    Filed: November 4, 2021
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peng-Soon LIM, Chung-Liang Cheng, Huang-Lin Chao
  • Publication number: 20220195246
    Abstract: A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 23, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Liao, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Chen-Hao Wu, Huang-Lin Chao
  • Publication number: 20220181467
    Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor layer, a high-k gate dielectric layer disposed over the interfacial layer, where the high-k gate dielectric layer includes a first metal, a metal oxide layer disposed between the high-k gate dielectric layer and the interfacial layer, where the metal oxide layer is configured to form a dipole moment with the interfacial layer, and a metal gate stack disposed over the high-k gate dielectric layer. The metal oxide layer includes a second metal different from the first metal, and a concentration of the second metal decreases from a top surface of the high-k gate dielectric layer to the interface between the high-k gate dielectric layer and the interfacial layer.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 9, 2022
    Inventors: Hsueh Wen Tsau, Ziwei Fang, Huang-Lin Chao, Kuo-Liang Sung
  • Publication number: 20220157653
    Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a source/drain structure formed beside the gate structure. The structure also includes a contact structure formed over the source/drain structure. The structure also includes a dielectric structure extending into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung LIAO, Lin-Yu HUANG, Chia-Hao CHANG, Huang-Lin CHAO
  • Publication number: 20220077296
    Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang CHENG, Ziwei FANG, Chun-I WU, Huang-Lin CHAO
  • Patent number: 11267987
    Abstract: A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Liao, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Chen-Hao Wu, Huang-Lin Chao
  • Patent number: 11257923
    Abstract: A method includes removing a dummy gate structure to form a gate trench over a semiconductor layer, forming a high-k gate dielectric layer over an interfacial layer exposed in the gate trench, depositing a metal-containing precursor over the high-k gate dielectric layer to form a metal-containing layer, and subsequently depositing an aluminum-containing precursor over the metal-containing layer, where depositing the aluminum-containing precursor forms an aluminum oxide layer at an interface between the high-k gate dielectric layer and the interfacial layer and where the metal-containing precursor includes a metal different from aluminum. The method further includes, subsequent to depositing the aluminum-containing precursor, removing a portion of the metal-containing layer, depositing a work-function metal layer over a remaining portion of the metal-containing layer, and forming a bulk conductive layer over the work-function metal layer, resulting in a metal gate structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh Wen Tsau, Ziwei Fang, Huang-Lin Chao, Kuo-Liang Sung
  • Publication number: 20210384322
    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiang LIN, Teng-Chun TSAI, Huang-Lin CHAO, Akira MINEJI
  • Patent number: 11183574
    Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang, Chun-I Wu, Huang-Lin Chao
  • Patent number: 11177259
    Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, I-Ming Chang, Ziwei Fang, Huang-Lin Chao
  • Publication number: 20210351278
    Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.
    Type: Application
    Filed: April 12, 2021
    Publication date: November 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming LIN, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao
  • Patent number: 11164956
    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiang Lin, Teng-Chun Tsai, Akira Mineji, Huang-Lin Chao