Abstract: A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

Abstract: Disclosed are a far-infrared emitting material and its preparation method. The far-infrared emitting material includes zirconium monoxide and at least one natural silicate mineral soil; the far-infrared emitting material and its preparation method use at least two of the above materials as raw materials, which are mixed according to a specific proportion, sintered, and crushed into granules. In the preparation method, the material is sintered within a temperature range of 1100-1250° C. and evenly mixed to form a slurry by a ball mill. The slurry is dispersed by adding an additive when needed and finally sifted, baked, dried to form a dry powder which is sifted to form a far-infrared emitting material with high emissivity and wide wavelength in the range of 8-20 ?m.

Abstract: A semiconductor structure includes a first circuit region; a first inner seal ring at least partially surrounding the first circuit region; and an outer seal ring at least partially surrounding the first inner seal ring. The outer seal ring includes a first corner and a substantially triangular corner seal ring (CSR) structure at the first corner. The first inner seal ring includes a second corner adjacent to and spaced away from the CSR structure. The semiconductor structure further includes a first region between a first side of the first corner and a first side of the second corner that is parallel to the first side of the first corner, and multiple functional patterns in the first region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.

Abstract: A first die includes a plurality of first transistors. A first seal ring surrounds the first die in a top view. A second die that a plurality of second transistors. A second seal ring surrounds the second die in the top view. A plurality of conductive elements extends into both the first die and the second die in the top view. The conductive elements electrically interconnect the first die with the second die. A third seal ring surrounds, in the top view, the first die, the second die, and the conductive elements.

Abstract: An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.

Abstract: A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

Abstract: A semiconductor structure includes a first circuit region; a first inner seal ring at least partially surrounding the first circuit region; and an outer seal ring at least partially surrounding the first inner seal ring. The outer seal ring includes a first corner and a substantially triangular corner seal ring (CSR) structure at the first corner. The first inner seal ring includes a second corner adjacent to and spaced away from the CSR structure. The semiconductor structure further includes a first region between a first side of the first corner and a first side of the second corner that is parallel to the first side of the first corner, and multiple functional patterns in the first region.

Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

Abstract: A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.

Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

Abstract: A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Abstract: Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Abstract: A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Abstract: Described is a semiconductor device structure with improved iso-dense bias and methods of producing thereof. Non-functional patterns may be added to an integrated circuit layout design. These patterns may be located next to an isolated transistor or an array of densely-packed transistors in order to mitigate the iso-dense bias effects. Furthermore, the patterns can take on a variety of geometric shapes and sizes.

Abstract: Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.