Patents by Inventor Huang Wen
Huang Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11993512Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.Type: GrantFiled: March 14, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng, Yi-Chuan Teng
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Publication number: 20240161672Abstract: An electronic circuit including a plurality of common terminals, a first circuit, a second circuit, and a plurality of switch units is provided. The first circuit is configured to output display driving signals to data lines of a display panel via the common terminals. The second circuit is configured to receive fingerprint sensing signals from fingerprint sensing lines of the display panel via the common terminals. Each of the switch units includes a first terminal coupled to one of the common terminals and a plurality of second terminals coupled to the first circuit and the second circuit. The switch units are grouped into a plurality of groups, and each group corresponds to a fingerprint sensing channel of the second circuit.Type: ApplicationFiled: January 24, 2024Publication date: May 16, 2024Applicant: Novatek Microelectronics Corp.Inventors: Huan-Teng Cheng, Ting-Hsuan Hung, Tzu-Wen Hsieh, Wei-Lun Shih, Huang-Chin Tang
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Publication number: 20240111827Abstract: The present disclosure provides a matrix device and an operation method thereof. The matrix device includes a transpose circuit and a memory. The transpose circuit is configured to receive a first element string representing a native matrix from a matrix source, wherein all elements in the native matrix are arranged in the first element string in one of a “row-major manner” and a “column-major manner”. The transpose circuit transposes the first element string into a second element string, wherein the second element string is equivalent to an element string in which all elements of the native matrix are arranged in another one of the “row-major manner” and the “column-major manner”. The memory is coupled to the transpose circuit to receive the second element string.Type: ApplicationFiled: November 2, 2022Publication date: April 4, 2024Applicant: NEUCHIPS CORPORATIONInventors: Huang-Chih Kuo, YuShan Ruan, Jian-Wen Chen, Tzu-Jen Lo
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Publication number: 20240105813Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor channel region, a metal oxide layer disposed over the interfacial layer, a high-k gate dielectric layer disposed over the metal oxide layer, a metal halide layer disposed over the high-k gate dielectric layer, and a metal gate electrode disposed over the high-k gate dielectric layer. The metal oxide layer and the interfacial layer form a dipole moment. The metal oxide layer includes a first metal. The metal halide layer includes a second metal different from the first metal.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Hsueh Wen Tsau, Ziwei Fang, Huang-Lin Chao, Kuo-Liang Sung
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Patent number: 11942373Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.Type: GrantFiled: May 10, 2023Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
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Patent number: 11935452Abstract: An electronic circuit for operating with a display panel including touch sensors and fingerprint sensors is provided. The electronic circuit includes a first circuit, a second circuit, a third circuit, a first switch circuit and a control circuit. The first circuit generates display driving signals for driving the display panel. The second circuit receives fingerprint sensing signals from the fingerprint sensors. The third circuit determines a touch information according to touch sensing signals from the touch sensors. The first switch circuit includes a plurality of first switch units, each of the first switch units includes a first switch element and a second switch element. The control circuit controls the first switch circuit to transmit the display driving signals in a first time interval, controls the first switch circuit to transmit the fingerprint sensing signals in a second time interval, and controls the third circuit to receive the fingerprint sensing signals in a third time interval.Type: GrantFiled: February 17, 2023Date of Patent: March 19, 2024Assignee: Novatek Microelectronics Corp.Inventors: Huan-Teng Cheng, Ting-Hsuan Hung, Tzu-Wen Hsieh, Wei-Lun Shih, Huang-Chin Tang
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Patent number: 11908884Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.Type: GrantFiled: April 7, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chou, Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
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Publication number: 20240047310Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.Type: ApplicationFiled: October 23, 2023Publication date: February 8, 2024Inventors: YANG-CHE CHEN, CHEN-HUA LIN, HUANG-WEN TSENG, VICTOR CHIANG LIANG, CHWEN-MING LIU
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Patent number: 11854913Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.Type: GrantFiled: August 9, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Wei-Yu Chou, Hong-Seng Shue, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
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Patent number: 11837526Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.Type: GrantFiled: June 24, 2019Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
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Publication number: 20230387182Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Wei-Yu CHOU, Yang-Che CHEN, Chen-Hua LIN, Victor Chiang LIANG, Huang-Wen TSENG, Chwen-Ming LIU
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Patent number: 11804433Abstract: A semiconductor package structure and method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a connection layer formed on a metal base layer, at least one die unit formed on the connection layer, a metal pillar connecting the metal base layer and surrounding the die unit, and an interconnect structure overlaid onto the die unit and the metal pillar. Each die unit comprises at least one die attached onto the connection layer and surrounded by a molding structure. The interconnect structure includes a first interconnect layer overlaid onto the die unit and the metal pillar and a second interconnect layer formed on the first interconnect layer. The first and second interconnect layers comprise first and second metal layers being parallel with the top surface of the die unit. A projection of the metal layers overlaps an upper surface of the die.Type: GrantFiled: June 18, 2021Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
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Patent number: 11776919Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.Type: GrantFiled: August 5, 2022Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng
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Patent number: 11768793Abstract: A plug-in mobile peripheral component interconnect express module connector is disclosed, comprising a plastic body, and a first terminal set and a second terminal set disposed relatively in the plastic body. The plastic body includes transversely penetrated slots, an upper end surface of the slots has intermittently plural upper magazines, and a lower end surface has intermittently plural lower magazines. The first terminal set includes plural first elastic terminals inserted in the upper magazines, and the second terminal set includes plural second elastic terminals inserted in the lower magazines. Each first elastic terminal is opposed to each second elastic terminal, forming a holding gap. A motherboard is inserted between the first elastic terminals and the second elastic terminals from a side, and an MXM board is inserted between the first elastic terminals and the second elastic terminals from the other side.Type: GrantFiled: May 21, 2021Date of Patent: September 26, 2023Assignee: DUN-PU ELECTRONICS CO. LTD.Inventor: Huang-Wen Wang
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Patent number: 11721597Abstract: A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.Type: GrantFiled: August 30, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
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Patent number: 11672181Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.Type: GrantFiled: June 14, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huang-Wen Tseng, Cheng-Chou Wu, Che-Jui Chang
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Patent number: 11626343Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.Type: GrantFiled: October 28, 2019Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
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Publication number: 20230064152Abstract: A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: YANG-CHE CHEN, CHEN-HUA LIN, VICTOR CHIANG LIANG, HUANG-WEN TSENG, CHWEN-MING LIU
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Publication number: 20220406705Abstract: A semiconductor package structure and method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a connection layer formed on a metal base layer, at least one die unit formed on the connection layer, a metal pillar connecting the metal base layer and surrounding the die unit, and an interconnect structure overlaid onto the die unit and the metal pillar. Each die unit comprises at least one die attached onto the connection layer and surrounded by a molding structure. The interconnect structure includes a first interconnect layer overlaid onto the die unit and the metal pillar and a second interconnect layer formed on the first interconnect layer. The first and second interconnect layers comprise first and second metal layers being parallel with the top surface of the die unit. A projection of the metal layers overlaps an upper surface of the die.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: YANG-CHE CHEN, CHEN-HUA LIN, VICTOR CHIANG LIANG, HUANG-WEN TSENG, CHWEN-MING LIU
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Publication number: 20220384281Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Yang-Che CHEN, Chen-Hua LIN, Huang-Wen TSENG, Victor Chiang LIANG, Chwen-Ming LIU