Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.

Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.

Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.

Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Abstract: A semiconductor package structure and method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a connection layer formed on a metal base layer, at least one die unit formed on the connection layer, a metal pillar connecting the metal base layer and surrounding the die unit, and an interconnect structure overlaid onto the die unit and the metal pillar. Each die unit comprises at least one die attached onto the connection layer and surrounded by a molding structure. The interconnect structure includes a first interconnect layer overlaid onto the die unit and the metal pillar and a second interconnect layer formed on the first interconnect layer. The first and second interconnect layers comprise first and second metal layers being parallel with the top surface of the die unit. A projection of the metal layers overlaps an upper surface of the die.

Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

Abstract: A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.

Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.

Abstract: A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.

Abstract: A semiconductor package structure and method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a connection layer formed on a metal base layer, at least one die unit formed on the connection layer, a metal pillar connecting the metal base layer and surrounding the die unit, and an interconnect structure overlaid onto the die unit and the metal pillar. Each die unit comprises at least one die attached onto the connection layer and surrounded by a molding structure. The interconnect structure includes a first interconnect layer overlaid onto the die unit and the metal pillar and a second interconnect layer formed on the first interconnect layer. The first and second interconnect layers comprise first and second metal layers being parallel with the top surface of the die unit. A projection of the metal layers overlaps an upper surface of the die.

Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

Abstract: A semiconductor package structure includes a magnetic core, a molding surrounding the magnetic core, a first RDL under the magnetic core, a second RDL over the magnetic core, and a plurality of through vi as in the molding. The magnetic core has a first core surface and a second core surface opposite to the first core surface, The molding has a first molding surface and a second molding surface opposite to the first molding surface. The first molding surface is substantially aligned with the first core surface, and the second molding surface is substantially aligned with the second core surface. The first RDL includes a plurality of first conductive lines. The second RDL includes a plurality of second conductive lines. The through vias are coupled to the first conductive lines and the second conductive lines to form a coil surrounding the magnetic core.

Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicide-containing field effect transistor disposed in a periphery region and a floating gate non-volatile memory device disposed in a memory region. The floating gate non-volatile memory device is free of silicide. The floating gate non-volatile memory device includes a second source, a third source, a fourth source, a second drain, and a third drain. The floating gate non-volatile memory device also includes a first floating gate electrode associated with the second source, the second drain, and the third source, and a second floating gate electrode associated with the second source, the third drain, and the fourth source. The second source is disposed between the first and second floating gate electrodes with a constant width. Each of the third source and the fourth source has a width larger than the constant width of the second source.

Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.

Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.