Patents by Inventor Huang-Yi Huang
Huang-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11444028Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.Type: GrantFiled: December 16, 2019Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
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Publication number: 20220230884Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
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Patent number: 11295956Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.Type: GrantFiled: May 29, 2020Date of Patent: April 5, 2022Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
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Patent number: 11011611Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a conductive region made of silicon, germanium or a combination thereof. The semiconductor device structure also includes an insulating layer over the semiconductor substrate and a fill metal material layer in the insulating layer. In addition, the semiconductor device structure includes a nitrogen-containing metal silicide or germanide layer between the conductive region and the fill metal material layers.Type: GrantFiled: June 29, 2020Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Min-Hsiu Hung, Yi-Hsiang Chao, Kuan-Yu Yeh, Kan-Ju Lin, Chun-Wen Nieh, Huang-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
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Patent number: 10879075Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.Type: GrantFiled: April 27, 2020Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Jyh-Cherng Sheu, Huang-Yi Huang, Chih-Wei Chang, Chi On Chui
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Publication number: 20200335597Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.Type: ApplicationFiled: June 29, 2020Publication date: October 22, 2020Inventors: Min-Hsiu HUNG, Yi-Hsiang CHAO, Kuan-Yu YEH, Kan-Ju LIN, Chun-Wen NIEH, Huang-Yi HUANG, Chih-Wei CHANG, Ching-Hwanq SU
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Publication number: 20200294807Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.Type: ApplicationFiled: May 29, 2020Publication date: September 17, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei CHANG, Kao-Feng LIN, Min-Hsiu HUNG, Yi-Hsiang CHAO, Huang-Yi HUANG, Yu-Ting LIN
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Publication number: 20200258746Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Inventors: Sung-Li Wang, Jyh-Cherng Sheu, Huang-Yi Huang, Chih-Wei Chang, Chi On Chui
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Patent number: 10714334Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.Type: GrantFiled: January 2, 2018Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Huang-Yi Huang, Chun-chieh Wang, Yu-Ting Lin, Min-Hsiu Hung
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Patent number: 10700177Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.Type: GrantFiled: April 27, 2018Date of Patent: June 30, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Min-Hsiu Hung, Yi-Hsiang Chao, Kuan-Yu Yeh, Kan-Ju Lin, Chun-Wen Nieh, Huang-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
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Patent number: 10685842Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.Type: GrantFiled: May 18, 2018Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
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Patent number: 10658234Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.Type: GrantFiled: July 29, 2016Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Min-Hsiu Hung, Sung-Li Wang, Pei-Wen Wu, Yida Li, Chih-Wei Chang, Huang-Yi Huang, Cheng-Tung Lin, Jyh-Cherng Sheu, Yee-Chia Yeo, Chi-On Chui
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Patent number: 10636664Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.Type: GrantFiled: October 11, 2019Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Jyh-Cherng Sheu, Huang-Yi Huang, Chih-Wei Chang, Chi On Chui
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Publication number: 20200118935Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Hong-Mao LEE, Huicheng CHANG, Chia-Han LAI, Chi-Hsuan NI, Cheng-Tung LIN, Huang-Yi HUANG, Chi-Yuan CHEN, Li-Ting WANG, Teng-Chun TSAI, Wei-Jung LIN
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Publication number: 20200043738Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Inventors: Sung-Li Wang, Jyh-Cherng Sheu, Huang-Yi Huang, Chih-Wei Chang, Chi On Chui
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Publication number: 20200006058Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.Type: ApplicationFiled: September 12, 2019Publication date: January 2, 2020Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Huang-Yi Huang, Chun-Chieh Wang, Yu-Ting Lin
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Patent number: 10510664Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.Type: GrantFiled: August 14, 2017Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
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Publication number: 20190355585Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.Type: ApplicationFiled: May 18, 2018Publication date: November 21, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei CHANG, Kao-Feng LIN, Min-Hsiu HUNG, Yi-Hsiang CHAO, Huang-Yi HUANG, Yu-Ting LIN
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Patent number: 10475654Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.Type: GrantFiled: August 31, 2017Date of Patent: November 12, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Jyh-Cherng Sheu, Huang-Yi Huang, Chih-Wei Chang, Chi On Chui
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Patent number: 10468260Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.Type: GrantFiled: November 30, 2018Date of Patent: November 5, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Jyh-Cherng Sheu, Huang-Yi Huang, Chih-Wei Chang, Chi On Chui