Abstract: A driver circuit includes a logic control component and a plurality of pins coupled to the logic control component. The plurality of pins include a clock pin, a data pin and at least two output pins. The clock pin is configured to receive a clock signal. The data pin is configured to receive, under control of the logic control component, a data signal in a period of an active level of the clock signal. The logic control component is configured to generate a driving control signal corresponding to each output pin according to the data signal, so as to control an electrical signal flowing through the output pin.

Abstract: A display device and a driving circuit thereof, and a driving method are provided, belonging to the field of display technologies. In the driving circuit, a light emission control sub-circuit may generate a driving signal and output the same from an output pin, so that a light-emitting unit group emits light based on the driving signal and a power supply signal provided by a power supply terminal. An amplification sub-circuit may amplify a reference power source signal provided by a reference power source terminal to have a voltage not less than a voltage of the power supply signal and transmit the amplified reference power source signal to a low-grayscale control sub-circuit. The low-grayscale control sub-circuit may control an on-off between the amplification sub-circuit and the output pin under the control of an enabling control terminal.

Abstract: A driver circuit includes a logic control component and a plurality of pins coupled to the logic control component. The plurality of pins include a clock pin, a data pin and at least two output pins. The clock pin is configured to receive a clock signal. The data pin is configured to receive, under control of the logic control component, a data signal in a period of an active level of the clock signal. The logic control component is configured to generate a driving control signal corresponding to each output pin according to the data signal, so as to control an electrical signal flowing through the output pin.

Abstract: The present application provides an array substrate and a display device. The array substrate includes a base, a first insulating layer located on the base, a first conductive layer located on the first insulating layer, a second insulating layer located on the first conductive layer, and an electronic element located on the first conductive layer. The first insulating layer is provided with a plurality of first openings. The first conductive layer includes a plurality of pads, each of which is at least partially located in one of the first openings. The second insulating layer is provided with a plurality of second openings. An orthographic projection of each first opening on the base falls into that of one of the second openings on the base. The electronic element includes an electronic element body, and a plurality of pins located on a side of the electronic element body toward the base.

Abstract: A driver circuit includes a logic control component and a plurality of pins coupled to the logic control component. The plurality of pins include a clock pin, a data pin and at least two output pins. The clock pin is configured to receive a clock signal. The data pin is configured to receive, under control of the logic control component, a data signal in a period of an active level of the clock signal. The logic control component is configured to generate a driving control signal corresponding to each output pin according to the data signal, so as to control an electrical signal flowing through the output pin.