Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches for receiving a first input signal and the second latch signal, and generating a scan data output signal depending on a trig signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the trig signal.

Abstract: A system having master and slave devices and communicating over an I2C bus has SDA and a SCL lines that are normally high unless a device pulls the voltage of the line Low. Normal data signals on the SDA line are set during the low phase of the clock signals on the SCL line and transferred to a receiver during the high phase of the clock signals. A slave device provides an alert signal on the SDA line during the low phase of the clock signals to send an alert signal to the master device. The alert signal may be a pulse signaling the slave device wakeup or a pulse pattern identifying the alerting slave device.

Abstract: An integrated circuit receives test-control information that is phase encoded on a scan clock used for testing a scan chain within the IC. The phase encoding does not affect the normal use of the scan clock and scan test chain and allows additional test-related data such as power supply, clock, and additional global and specialized status data to be collected by a secondary test data storage system such as a shift register. The phase encoding further controls selectively outputting the enhanced test status or the traditional scan test outputs.

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches for receiving a first input signal and the second latch signal, and generating a scan data output signal depending on a trig signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the trig signal.

Abstract: A system having master and slave devices and communicating over an I2C bus has SDA and a SCL lines that are normally high unless a device pulls the voltage of the line Low. Normal data signals on the SDA line are set during the low phase of the clock signals on the SCL line and transferred to a receiver during the high phase of the clock signals. A slave device provides an alert signal on the SDA line during the low phase of the clock signals to send an alert signal to the master device. The alert signal may be a pulse signaling the slave device wakeup or a pulse pattern identifying the alerting slave device.

Abstract: Test circuitry for an integrated circuit (IC) that has a scan chain includes a control unit for applying a test pattern and a clock signal to the scan chain, and for varying the level of a supply voltage during a scan test procedure. In a first test phase, the supply voltage is set to the rated voltage level of the IC while a test pattern is shifted into the scan chain at a fast rate. A second, capture phase is run at a lower rate and the supply voltage is reduced to a lower level such that defects that cannot be detected when the capture phase is run at the rated voltage are observable yet switching elements in the IC still function correctly. Running the shift phase at the higher speed reduces the overall test time compared with known very low voltage (VLV) scan test procedures.

Abstract: An integrated circuit receives test-control information that is phase encoded on a scan clock used for testing a scan chain within the IC. The phase encoding does not affect the normal use of the scan clock and scan test chain and allows additional test-related data such as power supply, clock, and additional global and specialized status data to be collected by a secondary test data storage system such as a shift register. The phase encoding further controls selectively outputting the enhanced test status or the traditional scan test outputs.

Abstract: Test circuitry for an integrated circuit (IC) that has a scan chain includes a control unit for applying a test pattern and a clock signal to the scan chain, and for varying the level of a supply voltage during a scan test procedure. In a first test phase, the supply voltage is set to the rated voltage level of the IC while a test pattern is shifted into the scan chain at a fast rate. A second, capture phase is run at a lower rate and the supply voltage is reduced to a lower level such that defects that cannot be detected when the capture phase is run at the rated voltage are observable yet switching elements in the IC still function correctly. Running the shift phase at the higher speed reduces the overall test time compared with known very low voltage (VLV) scan test procedures.

Abstract: An electronic design automation (EDA) tool for increasing the fault coverage of an integrated circuit (IC) design includes a processor that inserts at least one XOR gate, an AND gate, an OR gate and a multiplexer between observation test points and an existing first scan flip-flop of the IC design. The XOR gate provides an observation test signal to the first scan flip-flop by way of the AND gate, the OR gate, and the multiplexer such that the observation test signal covers the presence of faults at the observation test points. The first scan flip-flop outputs a data input signal, a set of test patterns, and a first set of test signals based on the observation test signal to indicate whether the IC design is faulty or not. A testable IC that can be structurally tested is fabricated using the IC design.

Abstract: A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.

Abstract: A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.