Abstract: A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

Abstract: An electronic device is provided in this disclosure. The electronic device includes a display panel, a transmission line, a universal motherboard, and an optional panel power management module. The display panel is a first type display panel or a second type display panel. The transmission line is a first transmission line or a second transmission line. The universal motherboard is connected to the first type display panel through the first transmission line, or connected to the second type display panel through the second transmission line. When the display panel is the first type display panel, the panel power management module is connected to the universal motherboard and the first type display panel through the first transmission line, so that the panel power management module provides power management required for the first type display panel according to the universal motherboard.

Abstract: A signal transmission device includes a first master signal conversion circuit and at least one first slave signal conversion circuit. The first master signal conversion circuit is configured to receive first partial data of output data from a data generation unit, convert the first partial data of the output data into a first transmission signal correspondingly, and output a first synchronization signal. The at least one first slave signal conversion circuit is configured to receive at least second partial data of the output data and convert the at least second partial data of the output data into at least one second transmission signal correspondingly, wherein the at least one first slave signal conversion circuit controls a timing of the at least one second transmission signal according to the first synchronization signal.

Abstract: A signal transmission device includes a first master signal conversion circuit and at least one first slave signal conversion circuit. The first master signal conversion circuit is configured to receive first partial data of output data from a data generation unit, convert the first partial data of the output data into a first transmission signal correspondingly, and output a first synchronization signal. The at least one first slave signal conversion circuit is configured to receive at least second partial data of the output data and convert the at least second partial data of the output data into at least one second transmission signal correspondingly, wherein the at least one first slave signal conversion circuit controls a timing of the at least one second transmission signal according to the first synchronization signal.

Abstract: A FIFO apparatus includes write registers, a first control circuit, a multiplexer, and a second control circuit. The write registers are for receiving an input signal and the first clock signal, and outputting first outputs to a multiplexer. The first control circuit is for receiving a first clock signal, generating a first toggling pulse, and enabling the write registers according to a sequence. The second control circuit is for controlling the multiplexer according to the first toggling pulse and a second clock. The multiplexer outputs a second output according to the sequence. The first and second clock signals have a first delay time and a second delay time, respectively. Difference between the first and second delay times is equal to M cycle(s) of the first clock signal, and a number of the write registers is equal to or larger than M.

Abstract: The present invention discloses an image processing circuit including an image processing unit, a frame rate adjusting circuit and a phase detection and control circuit. In operations of the image processing circuit, the image processing unit is configured to process an input image signal including a plurality of frames to generate a processed image signal including a plurality of processed frames, the frame rate adjusting circuit is configured to adjust a row number of vertical blanking intervals of at least one of the processed frames according to a control signal, to generate an output image signal including at least one adjusted frame, and the phase detection and control circuit is configured to determine a phase relationship of the input image signal or the processed image signal and the output image signal to generate the control signal.

Abstract: A FIFO apparatus includes write registers, a first control circuit, a multiplexer, and a second control circuit. The write registers are for receiving an input signal and the first clock signal, and outputting first outputs to a multiplexer. The first control circuit is for receiving a first clock signal, generating a first toggling pulse, and enabling the write registers according to a sequence. The second control circuit is for controlling the multiplexer according to the first toggling pulse and a second clock. The multiplexer outputs a second output according to the sequence. The first and second clock signals have a first delay time and a second delay time, respectively. Difference between the first and second delay times is equal to M cycle(s) of the first clock signal, and a number of the write registers is equal to or larger than M.

Abstract: A clock switching apparatus is provided. The clock input terminal receives a first clock signal as an input clock signal at first and start to receive a second clock signal as the input clock signal during a masking state of a masking signal within a clock-switching time period. The enabling synchronizing circuit receives a clock-switching enabling signal, receives the input clock signal and generate a synchronized enabling signal accordingly. The masking circuit receives the synchronized enabling signal and the mask signal to generate a final enabling signal. The output circuit receives the input clock signal, receive the final enabling signal that disables the output circuit only when either the masking signal is at the masking state or the synchronized enabling signal is at the clock-switching enabling state, and generate an output clock signal according to the input clock signal when the output circuit is enabled.

Abstract: A 3D modeling system is related. The 3D modeling system includes a light detection and ranging (LiDAR) device and a computer connected to the LiDAR device. The LiDAR device transmits detecting light and receive reflective light to form a reflective points data. The computer controls the work of the LiDAR device, processes the reflective points data, and builds a 3D model according to the reflective points data. The 3D modeling system does not need assistant sensor and has simple structure and low cost.

Abstract: A navigation system includes a navigation management module, a GPS navigation module, an LiDAR navigation module, an LiDAR navigation module and an environmental judgment module. The navigation management module is used to integrate and output navigation information and store map. The GPS navigation module is used to provide GPS navigation information to the navigation management module. The LiDAR navigation module is used to provide LiDAR information to the navigation management module. The environmental judgment module is used to determine whether the navigation system is indoors. The navigation management module is used to integrate and output different navigation information according to whether the navigation system is indoors.

Abstract: A navigation system includes a navigation management module, a GPS navigation module, an LiDAR navigation module, an LiDAR navigation module and an environmental judgment module. The navigation management module is used to integrate and output navigation information and store map. The GPS navigation module is used to provide GPS navigation information to the navigation management module. The LiDAR navigation module is used to provide LiDAR information to the navigation management module. The environmental judgment module is used to determine whether the navigation system is indoors. The navigation management module is used to integrate and output different navigation information according to whether the navigation system is indoors.

Abstract: A chip package structure including a carrier, a chip and a molding compound is provided. The chip is disposed on the carrier. The molding compound encapsulates a portion of the carrier and the chip. The top surface of the molding compound has a pin one dot and a pin gate contact. The pin one dot is located at a first corner on the top surface. The pin gate contact is located at a second corner except the first corner. The invention further provides a chip package mold chase and a chip package process using to form the chip package structure.

Abstract: A chip package structure including a carrier, a chip and a molding compound is provided. The chip is disposed on the carrier. The molding compound encapsulates a portion of the carrier and the chip. The top surface of the molding compound has a pin one dot and a pin gate contact. The pin one dot is located at a first corner on the top surface. The pin gate contact is located at a second corner except the first corner. The invention further provides a chip package mold chase and a chip package process using to form the chip package structure.

Abstract: A password input and verification method is provided to prevent the disclosing of the password from peeping. The method is easy to learn, transparent to the users, and requires no hardware change and only minor software modification. The method allows a user to enter a much longer string of characters when he or she is asked for the password. The user is then authenticated if the actual password is embedded as a whole anywhere within the input string. The method also provides a mechanism called prohibition key. A prohibition key is a predetermined character that, when present in the user input string, the user is not authenticated regardless of whether the actual password is contained in the input string or not.

Abstract: A stackable switch supporting redundant link and backup management. The stackable switch includes a stacking module, a processor and a management module. Several stackable switches can be stacked together in the form of a closed-loop link topology via the stacking module. The stacking module has an uplink port, a downlink port, and preferably a manual control device. The processor instructs the stacking module to enable or disable a downlink control bus within the downlink port when receiving a reconnect/disconnect command. If a link status, generated from the processor, indicates that these switches are stacked into the closed-loop link topology, the management module issues the disconnect command. Otherwise, the management module issues the reconnect command to recover a redundant link. Provided that the manual control device is activated, the management module in the same switch has the highest priority to become a master agent for the switch stack.

Abstract: A password input and verification method is provided to prevent the disclosing of the password from peeping. The method is easy to learn, transparent to the users, and requires no hardware change and only minor software modification. The method allows a user to enter a much longer string of characters when he or she is asked for the password. The user is then authenticated if the actual password is embedded as a whole anywhere within the input string. The method also provides a mechanism called prohibition key. A prohibition key is a predetermined character that, when present in the user input string, the user is not authenticated regardless of whether the actual password is contained in the input string or not.

Abstract: A stackable switch supporting redundant link and backup management. The stackable switch includes a stacking module, a processor and a management module. Several stackable switches can be stacked together in the form of a closed-loop link topology via the stacking module. The stacking module has an uplink port, a downlink port, and preferably a manual control device. The processor instructs the stacking module to enable or disable a downlink control bus within the downlink port when receiving a reconnect/disconnect command. If a link status, generated from the processor, indicates that these switches are stacked into the closed-loop link topology, the management module issues the disconnect command. Otherwise, the management module issues the reconnect command to recover a redundant link. Provided that the manual control device is activated, the management module in the same switch has the highest priority to become a master agent for the switch stack.