Abstract: The present disclosure discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of shift registers. An Nth-stage shift register of the plurality of shift registers includes a stage transmission signal selection module, a pull-up control module, a first filter module, a second filter module, a first output module, a first inverting module, an isolation module, or a second output module.

Abstract: The present application discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of cascaded gate drive units. Each of the gate drive units includes a stage transmission signal selection circuit, a pull-up control circuit, a pulse number reduction circuit, a first inversion circuit, a first output stage and a second output stage, and can output a second gate control signal with a greater number of pulses and a first gate control signal with a less number of pulses.

Abstract: A gate drive unit and a display device in which a plurality of cascaded gate drive circuits are electrically connected to a frequency-division control line configured to transmit a frequency-division control signal, so that a frequency-division control module in each gate drive circuit controls signal transmission between a first power supply terminal and a first node or a second node according to the frequency-division control signal, thereby controlling level states of gate control signals outputted by a first output module and a second output module.

Abstract: The present disclosure provides display panels and display devices. In the display panel, the through holes are designed, so that when the position of the through holes is offset, an overlapping area of any clock signal line and the through holes remains unchanged, and the overlapping area of each clock signal line and the through holes is the same, so that the parasitic capacitance of each clock signal line is similar or even equal, avoiding different signal delays of adjacent clock signal lines, and avoiding signal delay changes caused by impedance changes of the clock signal lines, so that the display panel can display normally.

Abstract: A gate driving circuit includes an input subcircuit, an output subcircuit and a voltage stabilizing subcircuit. The input subcircuit is configured to receive a start control signal and control a voltage of a second node. The output subcircuit is configured to output a gate driving signal according to a potential of the second node. The voltage stabilizing subcircuit is electrically connected to a first power line, a second power line and the second node, and is configured to transmit a voltage on the first power line or a voltage on the second power line to the second node in a low power consumption mode of the gate driving circuit.

Abstract: The present application provides a gate driver unit and a display panel, in which at least one of a first node control module and an output control module in a gate driver circuit at present stage is electrically connected to a second node of a gate drive circuit at a preceding stage, so as to ameliorate a problem that a voltage drop of a first gate control signal output by the gate drive circuit is large.

Abstract: A pixel driving circuit and a display panel may be provided. The pixel driving circuit may include: a driving transistor set to an N-type oxide semiconductor thin film transistor.

Abstract: The present application provides a gate driver unit and a display panel, in which at least one of a first node control module and an output control module in a gate driver circuit at present stage is electrically connected to a second node of a gate drive circuit at a preceding stage, so as to ameliorate a problem that a voltage drop of a first gate control signal output by the gate drive circuit is large.

Abstract: A display panel and a display device are provided by the present application. A first part and a second part of part of a first scanning signal line are connected through a third part, and/or a fourth part and a fifth part of part of the first scanning signal line are connected through a sixth part, so that a load of a hole-digging area is similar or even consistent with a load of other areas, thereby improving a display effect.

Abstract: The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

Abstract: The present application discloses a display panel including a quantity N of driver units that are cascaded. The quantity N of the driver units are arranged along a first direction. Each of the driver units includes a first output module, a signal generation module, and a second output module disposed along a second direction. The first output module is configured to output a first gate electrode driving signal. The second output module is configured to output a second gate electrode driving signal. The first gate electrode driving signal is different from the second gate electrode driving signal. The first output module includes a first buffer unit and a second buffer unit stacked on each other along a third direction. The present application stacks two buffer units in the first output module, which reduce a width of a frame occupied by the first output module while guaranteeing performance of transistors.

Abstract: The present application discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of cascaded gate drive units. Each of the gate drive units includes a stage transmission signal selection circuit, a pull-up control circuit, a pulse number reduction circuit, a first inversion circuit, a first output stage and a second output stage, and can output a second gate control signal with a greater number of pulses and a first gate control signal with a less number of pulses.

Abstract: This application discloses a gate driving circuit and a display panel. The gate driving circuit includes a plurality of stage circuits. The stage circuit includes an input module, a first output module, a second output module, a voltage stabilizing module, and a first driving control module. The voltage stabilizing module includes a first transistor whose gate receives a clock signal. When the gate driving circuit operates in a low power consumption mode, the clock signal turns on the first transistor to reduce a power consumption of the gate driving circuit by reducing a frequency of the clock signal.

Abstract: This application discloses a gate driving circuit and a display panel. The gate driving circuit includes a plurality of stage circuits. The stage circuit includes an input module, a first output module, a second output module, a voltage stabilizing module, and a first driving control module. The voltage stabilizing module includes a first transistor whose gate receives a clock signal. When the gate driving circuit operates in a low power consumption mode, the clock signal turns on the first transistor to reduce a power consumption of the gate driving circuit by reducing a frequency of the clock signal.

Abstract: The present application provides a pixel driving circuit and a display panel. The pixel driving circuit includes a driving transistor and a data writing module. a driving timing of the pixel driving circuit includes a writing frame including a first data writing phase and a second data writing phase in sequence, the data voltage includes an active data voltage and a first data compensation voltage, the data writing module is configured to write the first data compensation voltage into the gate, the first electrode, and the second electrode of the driving transistor in the first data writing phase, and to write the active data voltage into the gate, the first electrode, and the second electrode of the driving transistor in the second data writing phase.

Abstract: The present application provides a display panel and a display device. The display panel includes a display area and a non-display area, the display area including a first display partition and a second display partition arranged in a first direction; where, the display panel further includes: a substrate; a plurality of pixel driving circuits disposed on a side of the substrate and located in the display area; a gate driving circuit disposed on a side of the substrate and located in the non-display area on both sides of the display area in the first direction; a plurality of scanning lines disposed on a side of the substrate, where the gate driving circuit is electrically connected to the pixel driving circuits in the same first direction as corresponding one of the scanning lines via the corresponding scanning line.

Abstract: The present disclosure proposes a pixel circuit and a display panel. The pixel circuit includes a driving transistor, a light-emitting device, a feedback transistor, and a feedback capacitor. By coupling the feedback transistor and feedback capacitor between the gate of the driving transistor and the anode of the light-emitting device, the pixel circuit and display panel can make the voltage level of the gate of the driving transistor change correlatively with the voltage level of the anode of the light-emitting device. This can reduce the brightness change of the light-emitting device, and improves the brightness of the light-emitting device.

Abstract: The present disclosure discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of shift registers. An Nth-stage shift register of the plurality of shift registers includes a stage transmission signal selection module, a pull-up control module, a first filter module, a second filter module, a first output module, a first inverting module, an isolation module, or a second output module.

Abstract: The present application provides a display panel and a display terminal. The display panel includes a first metal layer having a plurality of first fan-out segments, and a third metal layer having a plurality of second fan-out segments, where the second fan-out segments extend in the same direction, the first fan-out segments and the second fan-out segments are located in a display area, one end of the first fan-out segment is electrically connected to one of the second fan-out segments.

Abstract: The present application discloses a display panel, which includes N GOA units disposed along a first direction. Each GOA unit includes a first output module, a signal generation module, and a second output module disposed along a second direction. The first output module is configured to output a first gate driving signal, and the second output module is configured to output a second gate driving signal. The first gate driving signal is different from the second gate driving signal, and a length of the first output module is different from a length of the second output module.