Patents by Inventor Huarong WANG

Huarong WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11860216
    Abstract: A fault arc signal detection method using a convolutional neural network, comprising: enabling a sampling signal subjected to analog-digital conversion to respectively pass through three different band-pass filters; respectively extracting a time-domain feature and a frequency-domain feature from a half wave output of each filter; constructing a two-dimensional feature matrix by means of extracted time-frequency feature vectors from the output of each filter, and stacking the feature matrices corresponding the outputs of the three filters to construct a three-dimensional matrix for each half wave; and processing a multi-channel feature matrix by using a multi-channel two-dimensional convolutional neural network, and determining, according to the output result of the neural network, whether the half wave is an arc.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: January 2, 2024
    Assignee: QINGDAO TOPSCOMM COMMUNICATION CO., LTD
    Inventors: Zhen Liu, Jianhua Wang, Yue Ma, Huarong Wang
  • Patent number: 11831138
    Abstract: A fault-arc identification method, device and apparatus, and a storage medium. The method comprises: performing sampling on a target arc at a high frequency, and obtaining a high-frequency sampling signal (S11); preprocessing the high-frequency sampling signal, and obtaining a processed sampling signal (S12); performing feature extraction on the processed sampling signal, and obtaining a target arc feature (S13); and inputting the target arc feature to a neural network model, obtaining a target output result, and determining, according to the target output result, whether the target arc is a fault-arc (S14). Performing sampling on a target arc at a high frequency can obtain more arc features from the target arc. Moreover, since a neural network model has favorable data classification capability, using a neural network model to perform determination with respect to the target arc can improve the accuracy and reliability of a fault-arc detection result.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: November 28, 2023
    Assignee: QINGDAO TOPSCOMM COMMUNICATION CO., LTD
    Inventors: Huarong Wang, Jianhua Wang, Yue Ma
  • Patent number: 11767506
    Abstract: Provided is a method for culturing immature oocytes. The method can promote in vitro maturation of the immature oocytes, and specifically comprises using follicular cells and a culture medium for culturing same. The culture medium for culturing the follicular cells contains CNP or variants thereof or analogues thereof and an HDAC (histone deacetylase) inhibitor. Also provided are the in vitro maturation culture medium containing CNP or variants thereof or analogues thereof and the HDAC inhibitor, and related compositions thereof, and the use of the above medium, culture medium and compositions in the promotion of in vitro maturation of the immature oocytes.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 26, 2023
    Assignee: CHINA AGRICULTURAL UNIVERSITY
    Inventors: Guoliang Xia, Chao Wang, Huarong Wang, Han Cai
  • Patent number: 11733286
    Abstract: A vector analysis calculation-based arc crosstalk signal identification method. A new sampling circuit manner is proposed in the method, wherein a current signal is sampled on zero and live lines, and the signal is converted into two digital signals with a sampling rate of 200 MHz by means of a dual-channel ADC, and the digital signals are sent to a hardware digital signal processing unit. Five pass bands are selected to perform band-pass filtering on the two signals separately. Time-sharing processing and vector analysis are performed on the filtered signals, and the amplitude ratio and fluctuation characteristics of two resistor terminal voltages, as well as the phase difference between shunt resistor and inductor terminal voltage signals are extracted as crosstalk feature quantities. According to a zero-crossing signal, a system segments the feature quantities extracted by a hardware processing module and sends same to a neural network for classification and determination.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: August 22, 2023
    Assignee: QINGDAO TOPSCOMM COMMUNICATION CO., LTD
    Inventors: Yue Ma, Jianhua Wang, Zhen Liu, Ze'an Jiang, Huarong Wang
  • Publication number: 20230160942
    Abstract: A fault arc signal detection method using a convolutional neural network, comprising: enabling a sampling signal subjected to analog-digital conversion to respectively pass through three different band-pass filters; respectively extracting a time-domain feature and a frequency-domain feature from a half wave output of each filter; constructing a two-dimensional feature matrix by means of extracted time-frequency feature vectors from the output of each filter, and stacking the feature matrices corresponding the outputs of the three filters to construct a three-dimensional matrix for each half wave; and processing a multi-channel feature matrix by using a multi-channel two-dimensional convolutional neural network, and determining, according to the output result of the neural network, whether the half wave is an arc.
    Type: Application
    Filed: December 25, 2020
    Publication date: May 25, 2023
    Applicant: QINGDAO TOPSCOMM COMMUNICATION CO., LTD
    Inventors: Zhen LIU, Jianhua WANG, Yue MA, Huarong WANG
  • Publication number: 20230022120
    Abstract: A vector analysis calculation-based arc crosstalk signal identification method. A new sampling circuit manner is proposed in the method, wherein a current signal is sampled on zero and live lines, and the signal is converted into two digital signals with a sampling rate of 200 MHz by means of a dual-channel ADC, and the digital signals are sent to a hardware digital signal processing unit. Five pass bands are selected to perform band-pass filtering on the two signals separately. Time-sharing processing and vector analysis are performed on the filtered signals, and the amplitude ratio and fluctuation characteristics of two resistor terminal voltages, as well as the phase difference between shunt resistor and inductor terminal voltage signals are extracted as crosstalk feature quantities. According to a zero-crossing signal, a system segments the feature quantities extracted by a hardware processing module and sends same to a neural network for classification and determination.
    Type: Application
    Filed: December 31, 2020
    Publication date: January 26, 2023
    Applicant: QINGDAO TOPSCOMM COMMUNICATION CO., LTD
    Inventors: Yue MA, Jianhua WANG, Zhen LIU, Ze'an JIANG, Huarong WANG
  • Publication number: 20220390501
    Abstract: A fault-arc identification method, device and apparatus, and a storage medium. The method comprises: performing sampling on a target arc at a high frequency, and obtaining a high-frequency sampling signal (S11); preprocessing the high-frequency sampling signal, and obtaining a processed sampling signal (S12); performing feature extraction on the processed sampling signal, and obtaining a target arc feature (S13); and inputting the target arc feature to a neural network model, obtaining a target output result, and determining, according to the target output result, whether the target arc is a fault-arc (S14). Performing sampling on a target arc at a high frequency can obtain more arc features from the target arc. Moreover, since a neural network model has favorable data classification capability, using a neural network model to perform determination with respect to the target arc can improve the accuracy and reliability of a fault-arc detection result.
    Type: Application
    Filed: December 24, 2020
    Publication date: December 8, 2022
    Applicant: QINGDAO TOPSCOMM COMMUNICATION CO., LTD
    Inventors: Huarong WANG, Jianhua WANG, Yue MA
  • Publication number: 20200224158
    Abstract: Provided is a method for culturing immature oocytes. The method can promote in vitro maturation of the immature oocytes, and specifically comprises using follicular cells and a culture medium for culturing same. The culture medium for culturing the follicular cells contains CNP or variants thereof or analogues thereof and an HDAC (histone deacetylase) inhibitor. Also provided are the in vitro maturation culture medium containing CNP or variants thereof or analogues thereof and the HDAC inhibitor, and related compositions thereof, and the use of the above medium, culture medium and compositions in the promotion of in vitro maturation of the immature oocytes.
    Type: Application
    Filed: October 13, 2017
    Publication date: July 16, 2020
    Applicant: CHINA AGRICULTURAL UNIVERSITY
    Inventors: Guoliang XIA, Chao WANG, Huarong WANG, Han CAI