Abstract: The present disclosure provides a trench field effect transistor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate (100), forming an epitaxial layer (101), forming a device trench (102) in the epitaxial layer, and forming a shielding dielectric layer (107), a shielding gate layer (105), a first isolation dielectric layer (108), a gate dielectric layer (109), a gate layer (110), a second isolation dielectric layer (112), a body region (114), a source (115), a source contact hole (118), a source electrode structure (122), and a drain electrode structure (123). During manufacturing of a trench field effect transistor structure, a self-alignment process is adopted in a manufacturing process, so that a cell pitch is not limited by an exposure capability and alignment accuracy of a lithography machine, to further reduce the cell pitch of the device, improve a cell density, and reduce a device channel resistance.

Abstract: The present disclosure provides a trench field effect transistor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate (100), forming an epitaxial layer (101), forming a device trench (102) in the epitaxial layer, and forming a shielding dielectric layer (107), a shielding gate layer (105), a first isolation dielectric layer (108), a gate dielectric layer (109), a gate layer (110), a second isolation dielectric layer (112), a body region (114), a source (115), a source contact hole (118), a source electrode structure (122), and a drain electrode structure (123). During manufacturing of a trench field effect transistor structure, a self-alignment process is adopted in a manufacturing process, so that a cell pitch is not limited by an exposure capability and alignment accuracy of a lithography machine, to further reduce the cell pitch of the device, improve a cell density, and reduce a device channel resistance.

Abstract: Provided is a method and device for controlling output arbitration, comprising: a received data stream is stored in a corresponding data cache queue according to a de-multiplexing filter condition, and data address information of the corresponding data cache queue is updated; when it is determined that a length of cache data in the data cache queue is greater than or equal to a fixed length, or when it is determined that the length of the cache data is less than the fixed length but the cache data contains an End Of Packet (EOP), the data cache queue is controlled to apply for output arbitration and the state of the data cache queue is updated; and the cache data in the data cache queue which applies for the output arbitration is outputted according to a preset scheduling rule and the state of the data cache queue.

Abstract: A cell processing method and device for a Switch Fabric (SF) chip are disclosed, which belong to the field of communications. The SF chip includes a unicast route table, which is multiplexed in two working modes and is looked up according to a unicast cell, and a multicast route table, which is multiplexed in the two working modes and is looked up according to a multicast cell. The cell processing method for an SF chip includes: the SF chip receives a cell and an input link number corresponding to the cell from an upstream apparatus and extracts a destination Identifier (ID) of the cell; the SF chip looks up a route table according to a working mode of the SF chip, the destination ID and the input link number to determine a first bitmap corresponding to the cell; and the SF chip performs load balancing on the first bitmap to obtain a second bitmap and outputs the cell to a downstream apparatus according to the second bitmap.

Abstract: A cell processing method and device for a Switch Fabric (SF) chip are disclosed, which belong to the field of communications. The SF chip includes a unicast route table, which is multiplexed in two working modes and is looked up according to a unicast cell, and a multicast route table, which is multiplexed in the two working modes and is looked up according to a multicast cell. The cell processing method for an SF chip includes: the SF chip receives a cell and an input link number corresponding to the cell from an upstream apparatus and extracts a destination Identifier (ID) of the cell; the SF chip looks up a route table according to a working mode of the SF chip, the destination ID and the input link number to determine a first bitmap corresponding to the cell; and the SF chip performs load balancing on the first bitmap to obtain a second bitmap and outputs the cell to a downstream apparatus according to the second bitmap.