Patents by Inventor Huatang LIN

Huatang LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10290705
    Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: May 14, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Feng Huang, Guangtao Han, Guipeng Sun, Feng Lin, Longjie Zhao, Huatang Lin, Bing Zhao
  • Publication number: 20180130877
    Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).
    Type: Application
    Filed: January 29, 2016
    Publication date: May 10, 2018
    Inventors: Feng HUANG, Guangtao HAN, Guipeng SUN, Feng LIN, Longjie ZHAO, Huatang LIN, Bing ZHAO
  • Patent number: 9865702
    Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 9, 2018
    Assignee: CSMC Technologies Fab2 Co., Ltd.
    Inventors: Feng Huang, Guangtao Han, Guipeng Sun, Feng Lin, Longjie Zhao, Huatang Lin, Bing Zhao, Lixiang Liu, Liangliang Ping, Fengying Chen
  • Publication number: 20170358657
    Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching
    Type: Application
    Filed: September 28, 2015
    Publication date: December 14, 2017
    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Feng HUANG, Guangtao HAN, Guipeng SUN, Feng LIN, Longjie ZHAO, Huatang LIN, Bing ZHAO, Lixiang LIU, Liangliang PING, Fengying CHEN