Abstract: This disclosure relates to a system that includes a boost circuit comprising a boost capacitor. The boost circuit is configured to provide a boost voltage at a first terminal of the boost capacitor by increasing the boost voltage at the first terminal to exceed a target voltage for a given charge cycle. A boost switch is configured to supply the boost voltage from the first terminal to a charge node for turning on a transistor, which is coupled to the charge node, based on a boost signal during the given charge cycle. A pull-down circuit is configured to control discharge of the charge node to a clamp voltage that is sufficient to turn off the transistor for the given charge cycle and to facilitate charging of the charge node in a next charge cycle.

Abstract: This disclosure relates to a system that includes a boost circuit comprising a boost capacitor. The boost circuit is configured to provide a boost voltage at a first terminal of the boost capacitor by increasing the boost voltage at the first terminal to exceed a target voltage for a given charge cycle. A boost switch is configured to supply the boost voltage from the first terminal to a charge node for turning on a transistor, which is coupled to the charge node, based on a boost signal during the given charge cycle. A pull-down circuit is configured to control discharge of the charge node to a clamp voltage that is sufficient to turn off the transistor for the given charge cycle and to facilitate charging of the charge node in a next charge cycle.

Abstract: An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.

Abstract: An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.

Abstract: An apparatus for equalizing channels is provided, which is generally transparent to link training. The apparatus generally includes equalization paths formed by an input circuit, a crossbar, and an output circuit and a controller. Each equalization path is coupled to at least one of the channels, and a controller has a VGA loop, a crossbar loop, and a driver loop. The AGC loop receives a first reference voltage and provides a gain control signal to the input circuit, and the gain control network comprises a replica of at least one of the equalization paths. The crossbar loop receives a second reference voltage and provides a crossbar control signal to the crossbar. The driver loop receives a third reference voltage and provides a driver control signal for the output circuit.

Abstract: An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.

Abstract: In versions 1.1a and 1.2 of the DISPLAYPORT™ standard, capacitors are used between a sourcing circuit and a switch for the auxiliary channel. As a result, these capacitors are generally uncharged when the switch activates the auxiliary channel, which can result in errors. Here, a switch is employed that uses precharge circuits to precharge these capacitors. Thus, errors due to charging of these capacitors can be reduced.

Abstract: An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.

Abstract: An apparatus for equalizing channels is provided, which is generally transparent to link training. The apparatus generally includes equalization paths formed by an input circuit, a crossbar, and an output circuit and a controller. Each equalization path is coupled to at least one of the channels, and a controller has a VGA loop, a crossbar loop, and a driver loop. The AGC loop receives a first reference voltage and provides a gain control signal to the input circuit, and the gain control network comprises a replica of at least one of the equalization paths. The crossbar loop receives a second reference voltage and provides a crossbar control signal to the crossbar. The driver loop receives a third reference voltage and provides a driver control signal for the output circuit.

Abstract: In versions 1.1a and 1.2 of the DISPLAYPORT™ standard, capacitors are used between a sourcing circuit and a switch for the auxiliary channel. As a result, these capacitors are generally uncharged when the switch activates the auxiliary channel, which can result in errors. Here, a switch is employed that uses precharge circuits to precharge these capacitors. Thus, errors due to charging of these capacitors can be reduced.

Abstract: In the many microelectronics applications, delays present in circuitry can affect both the design and the function of the circuitry. One example of delays impacting the function of a circuit is a relaxation oscillator, where delays present in comparator circuits and latches can cause its frequency to vary beyond desired ranges. Here, a relaxation circuit with delay compensation is described.

Abstract: In the many microelectronics applications, delays present in circuitry can affect both the design and the function of the circuitry. One example of delays impacting the function of a circuit is a relaxation oscillator, where delays present in comparator circuits and latches can cause its frequency to vary beyond desired ranges. Here, a relaxation circuit with delay compensation is described.

Abstract: A delay stage for a digital delay line comprising: a first string of delay segments coupled in series; a second string of delay segments coupled in series; pass gates coupled between the first string of delay segments and the second string of delay segments, wherein each delay segment in the first string of delay segments has an output coupled to an input of a corresponding one of the pass gates, and a corresponding delay segment in the second string of delay segments has an input coupled to an output of the corresponding one of the pass gates. The number of delay elements that make up the delay line is determined by selecting one of the pass gates.

Abstract: The delay locked loop (DLL) with skew adjustment inside the DLL includes: a Phase Detector; a delay line (Delay Stage 1, Delay Stage 2, and Delay Stage M) having an input coupled to a clock reference CLKREF; a first skew adjustment device dT1 coupled between the clock reference CLKREF and a first input of the Phase Detector; a second skew adjustment device dT2 coupled between an output of the delay line and a second input of the Phase Detector; a Slave Delay Stage for providing a delay to a strobe signal DQS; and a control voltage source (Charge Pump and Loop Filter) coupled to an output of the Phase Detector for controlling the delay line and the Slave Delay Stage in response to the Phase Detector.