Abstract: A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes.

Abstract: A patterning apparatus is provided. The patterning apparatus includes a plurality of liquid jet units arranged in one or more groups and configured to jet an anti-etching liquid onto a surface of a substrate. The patterning apparatus also includes a plurality of exposure units configured to expose light on the anti-etching liquid jetted on the surface of the substrate to heat and cure the jetted anti-etching liquid to form anti-etching patterns on the surface of the substrate. Further, the patterning apparatus includes a control unit configured to control motion status and jetting status of the plurality of liquid jet units and motion status and exposure status of the plurality of exposure units, so as to form the anti-etching patterns at a predetermined line width and thickness.

Abstract: The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat reservoir located under the wafer holder, but being separated from the wafer holder, for adjusting a temperature of the wafer holder based on the to-be-processed wafer; and a first driving unit connected to the heat reservoir for adjusting a distance between the wafer holder and the heat reservoir to adjust the temperature of the wafer holder.

Abstract: A photoresist coating apparatus is provided. The photoresist coating apparatus includes a base; and a position platform moving back and forth along a scanning direction on the base. The photoresist coating apparatus also includes an imprinter having a trench configured to hold photoresist and fixed on the position platform; and a photoresist spray nozzle disposed above the imprinter and configured to spray the photoresist into the trench. Further, the photoresist coating apparatus includes a reticle frame configured to install a cylindrical reticle and enable the cylindrical reticle to rotate around a center axis and contact with the imprinter so as to coat the photoresist in the trench on a surface of the cylindrical reticle.

Abstract: A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes.

Abstract: A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes.

Abstract: The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat reservoir located under the wafer holder, but being separated from the wafer holder, for adjusting a temperature of the wafer holder based on the to-be-processed wafer; and a first driving unit connected to the heat reservoir for adjusting a distance between the wafer holder and the heat reservoir to adjust the temperature of the wafer holder.

Abstract: A lithographic method includes forming a photoresist layer on a target layer, forming a photo-decomposable base (PDB) layer on the photo resist layer, performing an exposure operation using a mask, and performing a negative development treatment to form a patterned photoresist layer on the target layer. In some cases, the photo-decomposable base layer includes a self-generating top coating photo-decomposable base (TC-PDB) layer. The method can also include forming a top surface water-resistant coating in separate coating process. In some embodiments, a top surface water-resistant coating is self-generated during a photoresist coating process.

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a semiconductor substrate; and forming a plurality of semiconductor devices on the semiconductor substrate. The method also includes forming a dielectric layer covering the plurality of the semiconductor devices on the semiconductor substrate; and forming an optical auxiliary layer configured to reflect a portion of a levelness-detecting light and absorb a portion of the levelness detecting light transmitting through the optical auxiliary layer during a levelness-detecting process over the dielectric layer. Further, the method includes forming a photoresist layer over the optical auxiliary layer; and detecting a levelness of the semiconductor substrate and exposing the photoresist layer to form a patterned photoresist layer.

Abstract: An exposure apparatus is provided for performing a column scan-exposure process. The exposure apparatus includes a base for supporting the exposure apparatus; and a reticle stage configured for holding a reticle having at two mask pattern regions and carrying the reticle to move reciprocally along a scanning direction. The exposure apparatus also includes a wafer stage configured for holding a wafer and carrying the wafer to move reciprocally along the scanning direction. Further, the exposure apparatus includes a control unit configured to control the reticle stage and the wafer stage to cooperatively move to cause the at least two mask pattern regions of the reticle on the reticle stage to be continuously and sequentially projected on at least two corresponding exposure shots of the wafer on the wafer stage along the scanning direction to perform a column scan-exposure process.

Abstract: A patterning apparatus is provided. The patterning apparatus includes a plurality of liquid jet units arranged in one or more groups and configured to jet an anti-etching liquid onto a surface of a substrate. The patterning apparatus also includes a plurality of exposure units configured to expose light on the anti-etching liquid jetted on the surface of the substrate to heat and cure the jetted anti-etching liquid to form anti-etching patterns on the surface of the substrate. Further, the patterning apparatus includes a control unit configured to control motion status and jetting status of the plurality of liquid jet units and motion status and exposure status of the plurality of exposure units, so as to form the anti-etching patterns at a predetermined line width and thickness.

Abstract: The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat reservoir located under the wafer holder, but being separated from the wafer holder, for adjusting a temperature of the wafer holder based on the to-be-processed wafer; and a first driving unit connected to the heat reservoir for adjusting a distance between the wafer holder and the heat reservoir to adjust the temperature of the wafer holder.

Abstract: A patterning apparatus is provided. The patterning apparatus includes a plurality of liquid jet units arranged in one or more groups and configured to jet an anti-etching liquid onto a surface of a substrate. The patterning apparatus also includes a plurality of exposure units configured to expose light on the anti-etching liquid jetted on the surface of the substrate to heat and cure the jetted anti-etching liquid to form anti-etching patterns on the surface of the substrate. Further, the patterning apparatus includes a control unit configured to control motion status and jetting status of the plurality of liquid jet units and motion status and exposure status of the plurality of exposure units, so as to form the anti-etching patterns at a predetermined line width and thickness.

Abstract: A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes.

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a semiconductor substrate; and forming a plurality of semiconductor devices on the semiconductor substrate. The method also includes forming a dielectric layer covering the plurality of the semiconductor devices on the semiconductor substrate; and forming an optical auxiliary layer configured to reflect a portion of a levelness-detecting light and absorb a portion of the levelness detecting light transmitting through the optical auxiliary layer during a levelness-detecting process over the dielectric layer. Further, the method includes forming a photoresist layer over the optical auxiliary layer; and detecting a levelness of the semiconductor substrate and exposing the photoresist layer to form a patterned photoresist layer.

Abstract: An exposure apparatus is provided for performing an unidirectional scan-exposure. The exposure apparatus includes a base and a wafer stage group having a plurality of wafer stages on the base for holding wafers and successively moving from a first position to a second position of the base cyclically. The exposure apparatus also includes an alignment detection unit above the first position for detecting wafer stage fiducials at the first position and alignment marks on a wafer on the wafer stage to align the wafer. Further, the exposure apparatus includes a reticle stage on the second position for loading a cylindrical reticle and causing the cylindrical reticle to rotate around the center axis of the reticle stage and an optical projection unit between the reticle stage and the base for projecting light passing through the cylindrical reticle onto exposure regions on a wafer on the wafer stage.

Abstract: A lithographic method includes forming a photoresist layer on a target layer, forming a photo-decomposable base (PDB) layer on the photo resist layer, performing an exposure operation using a mask, and performing a negative development treatment to form a patterned photoresist layer on the target layer. In some cases, the photo-decomposable base layer includes a self-generating top coating photo-decomposable base (TC-PDB) layer. The method can also include forming a top surface water-resistant coating in separate coating process. In some embodiments, a top surface water-resistant coating is self-generated during a photoresist coating process.

Abstract: The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat reservoir located under the wafer holder, but being separated from the wafer holder, for adjusting a temperature of the wafer holder based on the to-be-processed wafer; and a first driving unit connected to the heat reservoir for adjusting a distance between the wafer holder and the heat reservoir to adjust the temperature of the wafer holder.

Abstract: A patterning apparatus is provided. The patterning apparatus includes a plurality of liquid jet units arranged in one or more groups and configured to jet an anti-etching liquid onto a surface of a substrate. The patterning apparatus also includes a plurality of exposure units configured to expose light on the anti-etching liquid jetted on the surface of the substrate to heat and cure the jetted anti-etching liquid to form anti-etching patterns on the surface of the substrate. Further, the patterning apparatus includes a control unit configured to control motion status and jetting status of the plurality of liquid jet units and motion status and exposure status of the plurality of exposure units, so as to form the anti-etching patterns at a predetermined line width and thickness.

Abstract: An exposure apparatus is provided for performing a column scan-exposure process. The exposure apparatus includes a base for supporting the exposure apparatus; and a reticle stage configured for holding a reticle having at two mask pattern regions and carrying the reticle to move reciprocally along a scanning direction. The exposure apparatus also includes a wafer stage configured for holding a wafer and carrying the wafer to move reciprocally along the scanning direction. Further, the exposure apparatus includes a control unit configured to control the reticle stage and the wafer stage to cooperatively move to cause the at least two mask pattern regions of the reticle on the reticle stage to be continuously and sequentially projected on at least two corresponding exposure shots of the wafer on the wafer stage along the scanning direction to perform a column scan-exposure process.