Patents by Inventor Hubert Allen Vander Plas

Hubert Allen Vander Plas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Solder on a sloped surface
    Patent number: 6979906
    Abstract: A method for depositing a solder layer or solder bump on a sloped surface. The method includes etching a sloped surface on a planar semiconductor substrate, depositing a solder-wettable layer on the sloped surface, masking the wettabler layer with a coating layer to control the position of the solder deposition, and using an organic film to prevent the solder from being deposited at regions not above either the wettable layer or the coating layer. Also, a semiconductor device structure on which a solder layer or solder bump is formed exclusively on a sloped surface.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: December 27, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hubert Allen Vander Plas, Frank Berauer
  • Solder on a sloped surface
    Publication number: 20040180526
    Abstract: A method for depositing a solder layer or solder bump on a sloped surface. The method includes etching a sloped surface on a planar semiconductor substrate, depositing a solder-wettable layer on the sloped surface, masking the wettabler layer with a coating layer to control the position of the solder deposition, and using an organic film to prevent the solder from being deposited at regions not above either the wettable layer or the coating layer. Also, a semiconductor device structure on which a solder layer or solder bump is formed exclusively on a sloped surface.
    Type: Application
    Filed: October 30, 2003
    Publication date: September 16, 2004
    Inventors: Hubert Allen Vander Plas, Frank Berauer
  • Solder on a sloped surface
    Patent number: 6764937
    Abstract: A method for depositing a solder layer or solder bump on a sloped surface. The method includes etching a sloped surface on a planar semiconductor substrate, depositing a solder-wettable layer on the sloped surface, masking the wettabler layer with a coating layer to control the position of the solder deposition, and using an organic film to prevent the solder from being deposited at regions not above either the wettable layer or the coating layer. Also, a semiconductor device structure on which a solder layer or solder bump is formed exclusively on a sloped surface.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: July 20, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hubert Allen Vander Plas, Frank Berauer
  • Multiple redundant through hole electrical interconnects and method for forming the same
    Patent number: 6659592
    Abstract: An apparatus incorporating multiple electrical interconnects extending through a substrate (e.g., a silicon wafer), and a method of forming the same. The electrical interconnects convey electrical signals through the substrate to structures mounted on the front side of the substrate. A conductive layer can be used to selectively distribute the electrical signals to the structures. Accordingly, it is not necessary to route electrical signals to the front side of the substrate in order to convey the signals to the structures. A structure can be coupled to multiple electrical interconnects in order to convey electrical signals along redundant paths through the substrate to the structure, improving reliability should one of the electrical interconnects fail.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: December 9, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hubert Allen Vander Plas, Barry Craig Snyder, Ron Allen Hellekson, Alfred I-Tsung Pan
  • Multiple redundant through hole electrical interconnects and method for forming the same
    Publication number: 20030035027
    Abstract: An apparatus incorporating multiple electrical interconnects extending through a substrate (e.g., a silicon wafer), and a method of forming the same. The electrical interconnects convey electrical signals through the substrate to structures mounted on the front side of the substrate. A conductive layer can be used to selectively distribute the electrical signals to the structures. Accordingly, it is not necessary to route electrical signals to the front side of the substrate in order to convey the signals to the structures. A structure can be coupled to multiple electrical interconnects in order to convey electrical signals along redundant paths through the substrate to the structure, improving reliability should one of the electrical interconnects fail.
    Type: Application
    Filed: August 16, 2001
    Publication date: February 20, 2003
    Inventors: Hubert Allen Vander Plas, Barry Craig Snyder, Ron Allen Hellekson, Alfred I-Tsung Pan