Abstract: An electronic circuit including: a first branch, placed between two terminals of application of a D.C. voltage, including a series connection of a first constant current source, of a first diode-connected N-channel MOS transistor, of a first diode-connected P-channel MOS transistor, and of a second constant current source; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected as a current mirror on the first N-channel MOS transistor and of a second P-channel MOS transistor connected as a current mirror on the first P-channel transistor; and an input terminal connected between the first N-channel and P-channel transistors and an output terminal connected between the second N-channel and P-channel transistors.

Abstract: An electronic circuit including: a first branch, placed between two terminals of application of a D.C. voltage, including a series connection of a first constant current source, of a first diode-connected N-channel MOS transistor, of a first diode-connected P-channel MOS transistor, and of a second constant current source; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected as a current mirror on the first N-channel MOS transistor and of a second P-channel MOS transistor connected as a current mirror on the first P-channel transistor; and an input terminal connected between the first N-channel and P-channel transistors and an output terminal connected between the second N-channel and P-channel transistors.

Abstract: A decoding and error correcting method is applicable to a secured code word that may have an error relative to an initial secured code word. The method includes an error correcting step, and a decoding step using a decoding function. The decoding step may be carried out before the error correcting step, and includes applying the decoding function to the secured code word to obtain a secured decoded word containing a coded error. The method reduces the decoding and error correcting time of the secured code word.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: A decoding and error correcting method is applicable to a secured code word that may have an error relative to an initial secured code word. The method includes an error correcting step, and a decoding step using a decoding function. The decoding step may be carried out before the error correcting step, and includes applying the decoding function to the secured code word to obtain a secured decoded word containing a coded error. The method reduces the decoding and error correcting time of the secured code word.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.