Patents by Inventor Hubert Maier

Hubert Maier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9728480
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Patent number: 9490103
    Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Gudrun Stranzl, Markus Zundel, Hubert Maier
  • Patent number: 9490173
    Abstract: A method for processing a wafer including a plurality of chips is provided. The method may include: forming a trench in the wafer between the plurality of chips; forming a diffusion barrier layer at least over the sidewalls of the trench; forming encapsulation material over the plurality of chips and in the trench; and singularizing the plurality of chips from a side opposite the encapsulation material.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: November 8, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Hubert Maier
  • Publication number: 20160111255
    Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Inventors: Manfred Engelhardt, Gudrun Stranzl, Markus Zundel, Hubert Maier
  • Patent number: 9219011
    Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Gudrun Stranzl, Markus Zundel, Hubert Maier
  • Publication number: 20150235917
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 20, 2015
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Patent number: 9059182
    Abstract: An arrangement is employed in a semiconductor device having a semiconductor body, the semiconductor body having a surface. The arrangement includes a surface portion on which a first metallization layer is arranged, and an alignment pattern arranged between the surface portion and the first metallization layer.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: June 16, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hubert Maier, Thomas Detzel
  • Publication number: 20150115448
    Abstract: A method for processing a wafer including a plurality of chips is provided. The method may include: forming a trench in the wafer between the plurality of chips; forming a diffusion barrier layer at least over the sidewalls of the trench; forming encapsulation material over the plurality of chips and in the trench; and singularizing the plurality of chips from a side opposite the encapsulation material.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Applicant: Infineon Technologies AG
    Inventor: Hubert Maier
  • Publication number: 20150064879
    Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Inventors: Manfred Engelhardt, Gudrun Stranzl, Markus Zundel, Hubert Maier
  • Publication number: 20140117511
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Fister Schlemitz Silvana, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Patent number: 7834427
    Abstract: An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: November 16, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Detzel, Hubert Maier, Kai-Alexander Schreiber, Stefan Woehlert, Uwe Hoeckele
  • Patent number: 7718505
    Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: May 18, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Nicola Vannucci, Hubert Maier
  • Patent number: 7531439
    Abstract: Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: May 12, 2009
    Assignee: Infineon Technologies AG
    Inventors: Johann Rieger, Stefan Lipp, Hans Peter Zeindl, Thomas Detzel, Hubert Maier
  • Publication number: 20080315303
    Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Nicola Vannucci, Hubert Maier
  • Publication number: 20080179669
    Abstract: An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.
    Type: Application
    Filed: February 28, 2007
    Publication date: July 31, 2008
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Thomas Detzel, Hubert Maier, Kai-Alexander Schreiber, Stefan Woehlert, Uwe Hoeckele
  • Publication number: 20070063318
    Abstract: An arrangement is employed in a semiconductor device having a semiconductor body, the semiconductor body having a surface. The arrangement includes a surface portion on which a first metallization layer is arranged, and an alignment pattern arranged between the surface portion and the first metallization layer.
    Type: Application
    Filed: September 14, 2006
    Publication date: March 22, 2007
    Applicant: Infineon Technologies AG
    Inventors: Hubert Maier, Thomas Detzel
  • Publication number: 20060014371
    Abstract: Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.
    Type: Application
    Filed: May 26, 2005
    Publication date: January 19, 2006
    Inventors: Johann Rieger, Stefan Lipp, Hans Zeindl, Thomas Detzel, Hubert Maier
  • Patent number: 6605841
    Abstract: A field-effect-controllable semiconductor component and a method for fabricating an electrode of the component includes a semiconductor body having a first zone of a first conduction type, a second zone of a second conduction type disposed above the first zone, and at least one trench extending into the semiconductor body in a vertical direction through the second zone, applying a first insulation layer at least in a region of the second zone in the trench, applying a first layer of electrode material to the semiconductor body, applying an intermediate layer to the first layer, applying a second layer of electrode material to the intermediate layer, removing a portion of the second layer and of the intermediate layer to leave the intermediate layer and the second layer at least partly in the trench, and patterning the first layer.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: August 12, 2003
    Assignee: Infineon Technologies AG
    Inventors: Sven Lanzerstorfer, Hubert Maier
  • Publication number: 20020100923
    Abstract: A field-effect-controllable semiconductor component and a method for fabricating an electrode of the component includes a semiconductor body having a first zone of a first conduction type, a second zone of a second conduction type disposed above the first zone, and at least one trench extending into the semiconductor body in a vertical direction through the second zone, applying a first insulation layer at least in a region of the second zone in the trench, applying a first layer of electrode material to the semiconductor body, applying an intermediate layer to the first layer, applying a second layer of electrode material to the intermediate layer, removing a portion of the second layer and of the intermediate layer to leave the intermediate layer and the second layer at least partly in the trench, and patterning the first layer.
    Type: Application
    Filed: December 20, 2001
    Publication date: August 1, 2002
    Inventors: Sven Lanzerstorfer, Hubert Maier