Abstract: A memory includes a supply voltage generation circuit for providing a supply voltage to a plurality of SRAM cells of the memory during at least one mode of memory operation. The supply voltage generation circuit includes a first reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The first reference generation circuit provides a first voltage during an at least one mode of memory operation. The supply voltage generation circuit includes a second reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The second reference generation circuit provides a second voltage during the at least one mode of memory operation. The voltage generation circuit includes an output for providing a supply voltage to the plurality of cells during the at least one mode of memory operation.

Abstract: One example discloses a test-point access structure within a semiconductor, including: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; wherein the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal.

Abstract: An integrated circuit, can comprise a first power supply terminal configured to supply a first voltage, a second power supply terminal configured to supply a second voltage, a first supply monitor including a detector having a first input and a second input, and configured to provide a fault indicator based on a comparison between the first and second inputs, and switching circuitry configured to during a normal operating mode, couple a voltage derived from the first voltage to the first input and a voltage derived from the second voltage to the second input, and during a self-test mode, couple the voltage derived from the second voltage to the first input and the voltage derived from the first voltage to the second input.

Abstract: Integrated circuitry, such as a microcontroller, for controlling an electric motor includes circuitry for measuring a bi-directional current flowing within a coil of the electric motor. The current is sensed by an externally implemented current sensing element, such as a shunt resistor, to produce a differential voltage that is delivered to input pins of the microcontroller, which are protected by electrostatic discharge protection circuits. Current sources implemented within the microcontroller are coupled to the input pins, and work in concert with external resistors to shift the differential voltage so that it is maintained within an appropriate voltage operating range so that an accurate measurement of the bi-directional current can be made by the microcontroller.

Abstract: Integrated circuitry, such as a microcontroller, for controlling an electric motor includes circuitry for measuring a bi-directional current flowing within a coil of the electric motor. The current is sensed by an externally implemented current sensing element, such as a shunt resistor, to produce a differential voltage that is delivered to input pins of the microcontroller, which are protected by electrostatic discharge protection circuits. Current sources implemented within the microcontroller are coupled to the input pins, and work in concert with external resistors to shift the differential voltage so that it is maintained within an appropriate voltage operating range so that an accurate measurement of the bi-directional current can be made by the microcontroller.

Abstract: A system for a power switch of a multiphase power converter coupled to an inductive load including a test controller, a voltage sampling circuit, a processing circuit, and a converter. A test pulse is applied to power switches of the converter to generate a test current through the inductive load, which forward biases a body diode of a power switch during a freewheel portion after the test pulse is completed. The voltage across the body diode is sampled during the freewheel portion, and the voltage samples are converted to a voltage value and a slope value. The voltage and slope values are converted to an estimated temperature value based on a characterization of the inductive load and the body diode. The conversion may be performed by a lookup table that stores an estimated temperature value for each unique combination of the voltage and slope values.

Abstract: A system for a power switch of a multiphase power converter coupled to an inductive load including a test controller, a voltage sampling circuit, a processing circuit, and a converter. A test pulse is applied to power switches of the converter to generate a test current through the inductive load, which forward biases a body diode of a power switch during a freewheel portion after the test pulse is completed. The voltage across the body diode is sampled during the freewheel portion, and the voltage samples are converted to a voltage value and a slope value. The voltage and slope values are converted to an estimated temperature value based on a characterization of the inductive load and the body diode. The conversion may be performed by a lookup table that stores an estimated temperature value for each unique combination of the voltage and slope values.

Abstract: The disclosure relates to an integrated circuit comprising: a first voltage terminal; a second voltage terminal; and a plurality of logic cells, comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells and a spare subset of cells. Electrical connectors are arranged to: connect the gates of the regular subset of cells in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal.

Abstract: A SAR ADC is disclosed. The SAR ADC includes a plurality of SAR-capacitors. For each of the SAR-capacitors, a sampling-switching-block is configured to connect a first plate of the associated SAR-capacitor to either: v-ref-low, v-ref-high or an input-voltage. The SAR ADC also includes an offset-capacitor and an offset-switching-block configured to connect a first plate of the offset-capacitor to either: v-ref-low, or v-ref-high. The SAR ADC further includes a SAR machine configured to provide signals to the sampling-switching-blocks and the offset-switching-block in order to define a calibration-sampling-mode-of-operation, a calibration-conversion-mode-of-operation, a sampling-mode-of-operation and a conversion-mode-of-operation. A code converter is also includes and is configured to subtract the offset-value from the raw-digital-word in order to provide a digital-output-signal.

Abstract: A SAR ADC is disclosed. The SAR ADC includes a plurality of SAR-capacitors. For each of the SAR-capacitors, a sampling-switching-block is configured to connect a first plate of the associated SAR-capacitor to either: v-ref-low, v-ref-high or an input-voltage. The SAR ADC also includes an offset-capacitor and an offset-switching-block configured to connect a first plate of the offset-capacitor to either: v-ref-low, or v-ref-high. The SAR ADC further includes a SAR machine configured to provide signals to the sampling-switching-blocks and the offset-switching-block in order to define a calibration-sampling-mode-of-operation, a calibration-conversion-mode-of-operation, a sampling-mode-of-operation and a conversion-mode-of-operation. A code converter is also includes and is configured to subtract the offset-value from the raw-digital-word in order to provide a digital-output-signal.

Abstract: The disclosure relates to an integrated circuit comprising: a first voltage terminal; a second voltage terminal; and a plurality of logic cells, comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells and a spare subset of cells. Electrical connectors are arranged to: connect the gates of the regular subset of cells in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal.

Abstract: An oscillator circuit comprising at least a first component arranged to be statically calibrated to calibrate the oscillator circuit to achieve a symmetrical frequency/temperature profile for the oscillator circuit. The oscillator circuit further comprises at least one further component arranged to be dynamically calibrated to enable an oscillating frequency of the oscillator circuit to be dynamically adjusted, and at least one temperature compensation component arranged to receive at least one temperature indication for the oscillator circuit and to dynamically adjust the at least one further component based at least partly on the at least one received temperature indication. In some examples, the at least one temperature compensation component is arranged to dynamically adjust the at least one further component based on a standardized temperature compensation scheme.

Abstract: An oscillator circuit comprising at least a first component arranged to be statically calibrated to calibrate the oscillator circuit to achieve a symmetrical frequency/temperature profile for the oscillator circuit. The oscillator circuit further comprises at least one further component arranged to be dynamically calibrated to enable an oscillating frequency of the oscillator circuit to be dynamically adjusted, and at least one temperature compensation component arranged to receive at least one temperature indication for the oscillator circuit and to dynamically adjust the at least one further component based at least partly on the at least one received temperature indication. In some examples, the at least one temperature compensation component is arranged to dynamically adjust the at least one further component based on a standardized temperature compensation scheme.