Abstract: An apparatus and method for executing an atomic test and update instruction. For example, one embodiment of a processor comprises: a decoder to decode an atomic test and update (ATU) instruction having a first operand specifying a first value in a first storage location, a second operand specifying a second value in a second storage location, a third operand specifying a third value in a third storage location, and an opcode specifying a condition to be tested relative to the first and second values; and execution circuitry to perform a load lock operation to load the first value from the first storage location, the load lock operation to prevent access by another instruction before a result of the ATU instruction is stored, the execution circuitry to test a condition related the first value and the second value, wherein if the condition is met then the execution circuitry is to add the first value and the third value to generate a sum and to store the sum to the first storage location.

Abstract: An apparatus and method for executing an atomic test and update instruction. For example, one embodiment of a processor comprises: a decoder to decode an atomic test and update (ATU) instruction having a first operand specifying a first value in a first storage location, a second operand specifying a second value in a second storage location, a third operand specifying a third value in a third storage location, and an opcode specifying a condition to be tested relative to the first and second values; and execution circuitry to perform a load lock operation to load the first value from the first storage location, the load lock operation to prevent access by another instruction before a result of the ATU instruction is stored, the execution circuitry to test a condition related the first value and the second value, wherein if the condition is met then the execution circuitry is to add the first value and the third value to generate a sum and to store the sum to the first storage location.

Abstract: Techniques are disclosed to provide scalable spinlocks for non-uniform memory access (NUMA). In some examples, a global spinlock configured to protect access to a shareable resource is protected by multiple local spinlocks, which are each configured to control access to the global spinlock. In a multi-socket NUMA system, the global spinlock is allocated on one of the sockets, and the local spinlocks are distributed over the multiple sockets. In some embodiments, one local spinlock is allocated on each of the multiple sockets. In other embodiments, the multiple local spinlocks may be equally distributed over the NUMA sockets. When contention for the global spinlock is low, processes can attempt to directly acquire the global spinlock. In contrast, when contention for the global spinlock is high, processes need to first acquire one of the local spinlocks associated with the global spinlock before attempting to acquire the global spinlock.

Abstract: Techniques are disclosed to provide scalable spinlocks for non-uniform memory access (NUMA). In some examples, a global spinlock configured to protect access to a shareable resource is protected by multiple local spinlocks, which are each configured to control access to the global spinlock. In a multi-socket NUMA system, the global spinlock is allocated on one of the sockets, and the local spinlocks are distributed over the multiple sockets. In some embodiments, one local spinlock is allocated on each of the multiple sockets. In other embodiments, the multiple local spinlocks may be equally distributed over the NUMA sockets. When contention for the global spinlock is low, processes can attempt to directly acquire the global spinlock. In contrast, when contention for the global spinlock is high, processes need to first acquire one of the local spinlocks associated with the global spinlock before attempting to acquire the global spinlock.