Abstract: A network device of a communication network is configured to implement a switch fabric that includes collector-based cell reordering functionality. In one embodiment, the switch fabric comprises a plurality of distributors, a plurality of routing elements each having inputs coupled to respective outputs of multiple ones of the distributors, and a plurality of collectors each having inputs coupled to respective outputs of multiple ones of the routing elements. At least a given one of the collectors comprises a sorting circuit configured to reorder streams of cells received from respective ones of the routing elements into a single reordered stream of cells utilizing a merge sort.

Abstract: A network device of a communication network is configured to implement a switch fabric that includes collector-based cell reordering functionality. In one embodiment, the switch fabric comprises a plurality of distributors, a plurality of routing elements each having inputs coupled to respective outputs of multiple ones of the distributors, and a plurality of collectors each having inputs coupled to respective outputs of multiple ones of the routing elements. At least a given one of the collectors comprises a sorting circuit configured to reorder streams of cells received from respective ones of the routing elements into a single reordered stream of cells utilizing a merge sort.

Abstract: A method comprising the steps of creating a random permutation of data from a data input by executing at least one of a Pseudo-Random Permutation (PRP) and a Pseudo-Random Function (PRF), creating a first data block by combining the random permutation of data with a received second data block and executing an ?-differentially uniform function on the result of the combination, XORing the result of the ?-DU function evaluation with a secret key, and reducing the first data block to a first message authentication code.

Abstract: Techniques are disclosed for in-line storage of message authentication codes with respective encrypted data blocks. In one aspect, a given data block is encrypted and a message authentication code is generated for the encrypted data block. A target address is determined for storage of the encrypted data block in a memory. The target address is then modified to permit in-line storage of the message authentication code with the encrypted data block in the memory, and the encrypted data block and the message authentication code are transferred to the memory for storage at the modified address. Illustrative embodiments of the techniques advantageously facilitate secure off-chip storage of data in a processing system.

Abstract: In a processing system comprising a processor and a plurality of peripherals coupled to the processor, access privileges of a secure operating mode of the processor are delegated to at least a given one of the peripherals. The given peripheral is configured to store, in a secure portion of that peripheral, state information indicative of the processor being in a secure operating mode. The given peripheral is further configured to utilize the stored state information to allow the given peripheral to access at least one resource that is accessible to the processor in the secure operating mode but is not otherwise accessible to the given peripheral. The processing system may comprise, for example, a system on a chip, wherein the processor and peripherals are combined into a single integrated circuit.

Abstract: A method comprising the steps of creating a random permutation of data from a data input by executing at least one of a Pseudo-Random Permutation (PRP) and a Pseudo-Random Function (PRF), creating a first data block by combining the random permutation of data with a received second data block and executing an ?-differentially uniform function on the result of the combination, XORing the result of the ?-DU function evaluation with a secret key, and reducing the first data block to a first message authentication code.

Abstract: A key update process applied to encrypted memory in a processing system determines an address from contents of a boundary register, reads an encrypted data block from a memory location specified by the address, decrypts the encrypted data block using a first key, re-encrypts the decrypted data block using a second key, writes the re-encrypted data block back to the memory location specified by the address, and updates the boundary register. These operations are repeated for one or more additional addresses. The boundary register contents are also used to determine appropriate keys for use in other read and write transactions to the memory. The key update process can be run as a background process, separate from the other read and write transactions to the memory, so as to incur minimal processing overhead.

Abstract: Techniques are disclosed for in-line storage of message authentication codes with respective encrypted data blocks. In one aspect, a given data block is encrypted and a message authentication code is generated for the encrypted data block. A target address is determined for storage of the encrypted data block in a memory. The target address is then modified to permit in-line storage of the message authentication code with the encrypted data block in the memory, and the encrypted data block and the message authentication code are transferred to the memory for storage at the modified address. Illustrative embodiments of the techniques advantageously facilitate secure off-chip storage of data in a processing system.

Abstract: In a processing system comprising a processor and a plurality of peripherals coupled to the processor, access privileges of a secure operating mode of the processor are delegated to at least a given one of the peripherals. The given peripheral is configured to store, in a secure portion of that peripheral, state information indicative of the processor being in a secure operating mode. The given peripheral is further configured to utilize the stored state information to allow the given peripheral to access at least one resource that is accessible to the processor in the secure operating mode but is not otherwise accessible to the given peripheral. The processing system may comprise, for example, a system on a chip, wherein the processor and peripherals are combined into a single integrated circuit.

Abstract: An exemplary method of confirming authorized use of a microcell base station includes determining that the microcell base station has made a connection with a mobile station. A determination is made whether the mobile station subsequently establishes a connection with a selected macrocell base station. Whether the mobile station successfully makes the connection with the selected macrocell base station is used as an indication of authorized use of the microcell base station.

Abstract: A method and apparatus are disclosed for reducing leakage power in a cache memory. A cache decay technique is employed for both data and instruction caches that removes power from cache lines that have not been accessed for a predefined time interval, referred to as the decay interval. The cache-line granularity of the present invention permits a significant reduction in leakage power while at the same time preserving much of the performance of the cache. The decay interval is maintained using a timer that is reset each time the corresponding cache line is accessed. The decay interval may be fixed or variable. Once the decay interval timer exceeds a specified decay interval, power to the cache line is removed. Once power to the cache line is removed, the contents of the data and tag fields are allowed to decay and the valid bit associated with the cache line is reset.

Abstract: Signaling information is communicated over an ATM link or other packet-based communication link using packet headers. The information may be, for example, telephony signaling information such as an on-hook/off-hook indicator, a ring/no-ring indicator, or any other type of information used in establishing, maintaining, terminating or otherwise configuring a telephony-based communication. In an illustrative embodiment, a single bit of signaling information is incorporated into a low order bit of a packet type indicator field in a header of an ATM user data cell. This low order bit, which is generally used as an End of Message (EOM) indicator in a cell which is part of a multi-cell message, can be used to transmit the signaling information in packets corresponding to single-cell messages.

Abstract: A method and apparatus are disclosed for reducing leakage power in a cache memory. A cache decay technique is employed for both data and instruction caches that removes power from cache lines that have not been accessed for a predefined time interval, referred to as the decay interval. The cache-line granularity of the present invention permits a significant reduction in leakage power while at the same time preserving much of the performance of the cache. The decay interval is maintained using a timer that is reset each time the corresponding cache line is accessed. The decay interval may be fixed or variable. Once the decay interval timer exceeds a specified decay interval, power to the cache line is removed. Once power to the cache line is removed, the contents of the data and tag fields are allowed to decay and the valid bit associated with the cache line is reset.

Abstract: An apparatus and method in digital processing provides a simple and efficient way of communicating parameters from a parent thread to child thread with two step thread creation. The method comprising the steps of: allocating hardware context for the child thread; enabling the parent thread to execute other instructions wherein parent thread register writes update both parent and child architectural registers; and spawning the child thread. In essence, the parent thread sends parameters to the child by writing to the parent's registers prior to spawning of the child thread.

Abstract: Line card control in an ATM or other packet-based switch is provided using an in-band device configuration in which control messages from a control processor of the switch are transmitted in one or more cells to a transmission convergence device in a line card. The transmission convergence device filters a stream of cells received in the line card in order to identify cells including control messages directed to the line card. The transmission convergence device then executes one or more commands associated with a given control message. Each control message may be transmitted in a single cell including a header and a payload. A message trailer portion of the payload may include device-specific data which specifies an interpretation of the payload structure. For example, the payload may include a series of commands, each including a read or write opcode, an address, and a data field.

Abstract: A circuit and a scheme for register renaming responsive to a thread ID register, comprises: a plurality of physical registers; a plurality of architectual registers; a rename logic circuit where every write to an architectual register of the plurality of architectural registers is assigned a new physical register of the plurality of physical registers; a register map circuit containing a corresponding entry for each of the plurality of architectual registers. The register map circuit is responsive to the thread ID register such that a different physical map is selected for architectual registers of each thread, whereby the plurality of architectual registers can be greater than the plurality of physical registers.