Abstract: A cyclic redundancy check generator for a high speed data bus is capable of outputting frames of data and cyclic redundancy check bits concatenated together without any additional space or time delay between frames while operating at a normal clock speed. Data to be transmitted is parallel loaded into series-connected registers via multiplexers connected between the registers. The multiplexers also provide parallel loading of the cyclic redundancy check bits for a frame of data from a look-ahead cyclic redundancy check logic circuit. The output of the logic circuit is also connected to a cyclic redundancy check register. The logic circuit has inputs connected to the final series-connected data register and the cyclic redundancy check register.