Patents by Inventor Hubert Teyssedre

Hubert Teyssedre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210217937
    Abstract: A method is provided for producing a microelectronic device having a subsequent grating of reliefs of which at least one wall is slanted, the method including providing a structure including a base, and an initial grating of reliefs, each relief having at least one proximal end in contact with the base, a distal end, and at least one wall extending between the proximal end and the distal end; and laying the reliefs of the initial grating on one another, by application of at least one stress on the structure, such that walls facing two adjacent reliefs come into contact, thus generating at least one subsequent grating of reliefs of which at least one wall is slanted.
    Type: Application
    Filed: November 18, 2020
    Publication date: July 15, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stefan LANDIS, Hubert TEYSSEDRE
  • Publication number: 20210072639
    Abstract: A process for transfer imprinting using a novel family of anti-sticking layers, such as for nanoimprint lithography processes, is described.
    Type: Application
    Filed: December 19, 2018
    Publication date: March 11, 2021
    Applicant: Arkema France
    Inventors: Christophe Navarro, Celia Nicolet, Xavier Chevalier, Florian Delachat, Hubert Teyssedre
  • Patent number: 10886239
    Abstract: A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 5, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stefan Landis, Hubert Teyssedre
  • Publication number: 20200135663
    Abstract: A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 30, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE AUX ENERGIES ALTERNATIVES
    Inventors: Stefan LANDIS, Hubert Teyssedre