Patents by Inventor Hubert Teyssedre
Hubert Teyssedre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103361Abstract: A process for transfer imprinting using a novel family of anti-sticking layers, such as for nanoimprint lithography processes, is described.Type: ApplicationFiled: November 14, 2023Publication date: March 28, 2024Applicant: Arkema FranceInventors: Christophe Navarro, Celia Nicolet, Xavier Chevalier, Florian Delachat, Hubert Teyssedre
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Patent number: 11880131Abstract: A process for transfer imprinting using a novel family of anti-sticking layers, such as for nanoimprint lithography processes, is described.Type: GrantFiled: December 19, 2018Date of Patent: January 23, 2024Assignee: Arkema FranceInventors: Christophe Navarro, Celia Nicolet, Xavier Chevalier, Florian Delachat, Hubert Teyssedre
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Publication number: 20220350252Abstract: A process for producing a hybrid structured surface, including depositing, on a substrate, a layer of mineral resin including a proportion of Si and/or of SiO2 includes between 1% and 30% by molar mass; forming a structure including a plurality of pattern motifs in that layer, having at least one dimension, measured parallel or perpendicular to the substrate, includes between 50 nm and 500 ?m; forming a roughness on at least part of the surface of the pattern motifs.Type: ApplicationFiled: April 21, 2022Publication date: November 3, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Hubert TEYSSEDRE, Nicolas POSSEME, Zouhir MEHREZ, Michael MAY
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Patent number: 11456403Abstract: A method is provided for producing a microelectronic device having a subsequent grating of reliefs of which at least one wall is slanted, the method including providing a structure including a base, and an initial grating of reliefs, each relief having at least one proximal end in contact with the base, a distal end, and at least one wall extending between the proximal end and the distal end; and laying the reliefs of the initial grating on one another, by application of at least one stress on the structure, such that walls facing two adjacent reliefs come into contact, thus generating at least one subsequent grating of reliefs of which at least one wall is slanted.Type: GrantFiled: November 18, 2020Date of Patent: September 27, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Stefan Landis, Hubert Teyssedre
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Patent number: 11444041Abstract: A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.Type: GrantFiled: March 30, 2021Date of Patent: September 13, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Hubert Teyssedre, Stefan Landis, Michael May
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Publication number: 20220111562Abstract: A method for producing a structure having at least one curved pattern includes providing a substrate having a front face, where one portion is structured by at least one plurality of reliefs, the reliefs of each plurality defining spaces therebetween, and another portion is free of reliefs. The method also includes depositing a base layer of a material such as a polymer or a glass, on the front face of the substrate, at least in line with the reliefs, and allowing the material of the base layer to at least partially fill the at least one of the spaces by deformation. The base layer is thus deformed so that its free surface has at least one curved pattern.Type: ApplicationFiled: July 23, 2019Publication date: April 14, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Hubert TEYSSEDRE, Pierre BRIANCEAU, Stefan LANDIS
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Publication number: 20220028802Abstract: The invention relates to a method for making an individualization zone of a microchip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a conductor layer (30A) comprising via holes (30), the method comprising the following steps: providing at least one dielectric layer (200, 201, 202) having a thickness hd, forming a metal mask layer (300) having a thickness hm and a residual stress ?r on the at least one dielectric layer (200, 201, 202), etching the layer (300) so as to form line patterns (310) of width l, etching the at least one dielectric layer (200, 201, 202) between the line patterns (310) so as to form trenches (210) separated by walls (211), filling the trenches (210) with an electrically conductive material so as to form the electrical tracks (10, 10KO) of the first level (10A), forming via holes (30, 30OK, 30KO1, 30KO2) of the conductor layer (30A), forming the second level (20A) of electrical tracks (20, 20OK), the method being characterized in that the thicknType: ApplicationFiled: July 21, 2021Publication date: January 27, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas POSSEME, Stefan LANDIS, Hubert TEYSSEDRE
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Publication number: 20210375794Abstract: A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.Type: ApplicationFiled: March 30, 2021Publication date: December 2, 2021Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Hubert Teyssedre, Stefan Landis, Michael May
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Publication number: 20210217937Abstract: A method is provided for producing a microelectronic device having a subsequent grating of reliefs of which at least one wall is slanted, the method including providing a structure including a base, and an initial grating of reliefs, each relief having at least one proximal end in contact with the base, a distal end, and at least one wall extending between the proximal end and the distal end; and laying the reliefs of the initial grating on one another, by application of at least one stress on the structure, such that walls facing two adjacent reliefs come into contact, thus generating at least one subsequent grating of reliefs of which at least one wall is slanted.Type: ApplicationFiled: November 18, 2020Publication date: July 15, 2021Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Stefan LANDIS, Hubert TEYSSEDRE
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Publication number: 20210072639Abstract: A process for transfer imprinting using a novel family of anti-sticking layers, such as for nanoimprint lithography processes, is described.Type: ApplicationFiled: December 19, 2018Publication date: March 11, 2021Applicant: Arkema FranceInventors: Christophe Navarro, Celia Nicolet, Xavier Chevalier, Florian Delachat, Hubert Teyssedre
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Patent number: 10886239Abstract: A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.Type: GrantFiled: October 29, 2019Date of Patent: January 5, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Stefan Landis, Hubert Teyssedre
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Publication number: 20200135663Abstract: A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.Type: ApplicationFiled: October 29, 2019Publication date: April 30, 2020Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE AUX ENERGIES ALTERNATIVESInventors: Stefan LANDIS, Hubert Teyssedre