Patents by Inventor Hubert Werthmann

Hubert Werthmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12125841
    Abstract: A semiconductor device includes a semiconductor body including an upper surface, input and output terminals disposed on the upper surface of the semiconductor body, first and second p-n junction devices that are monolithically integrated in the semiconductor body, and a signal line protection circuit connected between the input and output terminals and comprising a low-pass filter and a voltage clamping device, wherein each of the low-pass filter and the voltage clamping device include the first and second p-n junction devices.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: October 22, 2024
    Assignee: Infineon Technologies AG
    Inventors: Josef-Paul Schaffer, Hubert Werthmann, Juliane Laurer
  • Publication number: 20240038756
    Abstract: A semiconductor device includes a semiconductor body including an upper surface, input and output terminals disposed on the upper surface of the semiconductor body, first and second p-n junction devices that are monolithically integrated in the semiconductor body, and a signal line protection circuit connected between the input and output terminals and comprising a low-pass filter and a voltage clamping device, wherein each of the low-pass filter and the voltage clamping device include the first and second p-n junction devices.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Josef-Paul Schaffer, Hubert Werthmann, Juliane Laurer
  • Patent number: 9577852
    Abstract: A common-mode suppressor for eliminating common-mode noise in high frequency differential data transmission systems and an associated method includes a long coiled differential transmission line configured to transfer data between a source and a load. The differential transmission line comprises a first conductive wire and a second conductive wire which are inductively and capacitively coupled and are laterally aligned or vertically aligned with each other. Further, the differential transmission line is matched for differential signals and un-matched for common-mode noise.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Alexander Glas, Hubert Werthmann, Josef-Paul Schaffer, Francesca Arcioni, Gabriele Bettineschi
  • Patent number: 9548293
    Abstract: An ESD (electrostatic discharge) protection device includes a first III-nitride p-i-n diode and a second III-nitride p-i-n diode connected to the first III-nitride p-i-n diode in an antiparallel arrangement configured to provide voltage clamping at 5V or less under forward bias of either the first or second III-nitride p-i-n diode for transient current in both forward and reverse directions. A corresponding method of manufacturing the ESD protection device is also provided.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 17, 2017
    Assignee: Infineon Technologies AG
    Inventor: Hubert Werthmann
  • Publication number: 20160127157
    Abstract: A common-mode suppressor for eliminating common-mode noise in high frequency differential data transmission systems and an associated method includes a long coiled differential transmission line configured to transfer data between a source and a load. The differential transmission line comprises a first conductive wire and a second conductive wire which are inductively and capacitively coupled and are laterally aligned or vertically aligned with each other. Further, the differential transmission line is matched for differential signals and un-matched for common-mode noise.
    Type: Application
    Filed: November 3, 2014
    Publication date: May 5, 2016
    Inventors: Maciej Wojnowski, Alexander Glas, Hubert Werthmann, Josef-Paul Schaffer, Francesca Arcioni, Gabriele Bettineschi
  • Patent number: 9165828
    Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 20, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gabriele Bettineschi, Uwe Seidel, Wolfgang Walter, Michael Schrenk, Hubert Werthmann
  • Publication number: 20150236008
    Abstract: An ESD (electrostatic discharge) protection device includes a first III-nitride p-i-n diode and a second III-nitride p-i-n diode connected to the first III-nitride p-i-n diode in an antiparallel arrangement configured to provide voltage clamping at 5V or less under forward bias of either the first or second III-nitride p-i-n diode for transient current in both forward and reverse directions. A corresponding method of manufacturing the ESD protection device is also provided.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Inventor: Hubert Werthmann
  • Publication number: 20140127895
    Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.
    Type: Application
    Filed: January 13, 2014
    Publication date: May 8, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gabriele Bettineschi, Uwe Seidel, Wolfgang Walter, Michael Schrenk, Hubert Werthmann
  • Patent number: 8659118
    Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: February 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gabriele Bettineschi, Uwe Seidel, Wolfgang Walter, Michael Schrenk, Hubert Werthmann
  • Publication number: 20130026601
    Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.
    Type: Application
    Filed: July 29, 2011
    Publication date: January 31, 2013
    Applicant: Infineon Technologies AG
    Inventors: Gabriele Bettineschi, Uwe Seidel, Wolfgang Walter, Michael Schrenk, Hubert Werthmann
  • Patent number: 7307329
    Abstract: An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer including a guard ring in those areas of the surface and of the active layer which are adjacent to the insulating layer, and a contacting layer arranged on an area of the active layer, the contact layer being adjacent to an area of the guard ring. The device may be produced by a process of three-fold self-alignment, to be precise utilizing a spacer process by means of which a diffusion source having a lateral extension far below the lithography limit is made possible.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: December 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Cartens Ahrens, Ulf Bartl, Bernd Eisener, Wolfgang Hartung, Christian Herzum, Raimund Peichl, Stefan Pompl, Hubert Werthmann
  • Publication number: 20070085143
    Abstract: A semiconductor structure for draining an overvoltage pulse comprises a first semiconductor region having a first doping type and a semiconductor layer arranged adjacent the first semiconductor region. The semiconductor layer includes an isolation structure configured to electrically isolate a second semiconductor region from a surrounding region. The second semiconductor region has a second doping type. A third semiconductor region having the first doping type is arranged adjacent the second semiconductor region and is disposed within an area limited by the isolation structure. A first contacting structure is configured to provide an electrical contact with the first semiconductor region, and a second contacting structure is configured to provide an electrical contact with the third semiconductor region. The first and second semiconductor regions are more highly doped than the second semiconductor region.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 19, 2007
    Applicant: Infineon Technologies AG
    Inventors: Bernd Eisener, Hubert Werthmann
  • Patent number: 6949812
    Abstract: A semiconductor structure for high frequency operation has a substrate with a doped well formed therein and a buffer layer made of a substrate material covers the well. The buffer layer is made of an undoped material and is disposed on a top side of the well for inhibiting an outdiffusion of a dopant from the well. At least a portion of the substrate is not covered by the buffer layer.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: September 27, 2005
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Losehand, Hubert Werthmann
  • Patent number: 6873242
    Abstract: The magnetic component uses at least two different layers of magnetic material for carrying and amplifying the magnetic flux. The use of two different layers which may, however, have the same material composition allows the magnetic conductors to form a magnetic circuit with a locally matched domain alignment. The magnetic component accordingly allows considerable improvements to be achieved in the component parameter, in particular a considerable increase in the Q-factor.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: March 29, 2005
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Ulf Bartl, Wolfgang Hartung, Reinhard Losehand, Hubert Werthmann
  • Publication number: 20050035423
    Abstract: An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer including a guard ring in those areas of the surface and of the active layer which are adjacent to the insulating layer, and a contacting layer arranged on an area of the active layer, the contact layer being adjacent to an area of the guard ring. The device may be produced by a process of three-fold self-alignment, to be precise utilizing a spacer process by means of which a diffusion source having a lateral extension far below the lithography limit is made possible.
    Type: Application
    Filed: July 8, 2004
    Publication date: February 17, 2005
    Applicant: Infineon Technologies AG
    Inventors: Cartens Ahrens, Ulf Bartl, Bernd Eisener, Wolfgang Hartung, Christian Herzum, Raidmund Peichl, Stefan Pompl, Hubert Werthmann
  • Patent number: 6842083
    Abstract: A conductor network includes trimming capacitors and is connected in parallel with a resonant circuit. The trimming capacitors can be connected in parallel with the variable-capacitance diodes in the resonant circuit through PIN diodes, enabling trimming of the resonant circuit.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: January 11, 2005
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Losehand, Hubert Werthmann, Ulf Bartl
  • Publication number: 20040191569
    Abstract: The magnetic component uses at least two different layers of magnetic material for carrying and amplifying the magnetic flux. The use of two different layers which may, however, have the same material composition allows the magnetic conductors to form a magnetic circuit with a locally matched domain alignment. The magnetic component accordingly allows considerable improvements to be achieved in the component parameter, in particular a considerable increase in the Q-factor.
    Type: Application
    Filed: March 10, 2004
    Publication date: September 30, 2004
    Inventors: Carsten Ahrens, Ulf Bartl, Wolfgang Hartung, Reinhard Losehand, Hubert Werthmann
  • Patent number: 6551911
    Abstract: A method for producing Schottky diodes having a protective ring in an edge region of a Schottky contact. The protective ring is produced by a protective ring material that is deposited onto a surface of a semiconductor layer, which surface is provided with a patterned masking layer beforehand, and the protective ring material subsequently being siliconized. In this case, the protective ring material constitutes a metal, in particular a high barrier metal, which has, in particular, platinum.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: April 22, 2003
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Losehand, Hubert Werthmann
  • Publication number: 20030067362
    Abstract: A conductor network includes trimming capacitors and is connected in parallel with a resonant circuit. The trimming capacitors can be connected in parallel with the variable-capacitance diodes in the resonant circuit through PIN diodes, enabling trimming of the resonant circuit.
    Type: Application
    Filed: October 10, 2002
    Publication date: April 10, 2003
    Inventors: Reinhard Losehand, Hubert Werthmann, Ulf Bartl
  • Publication number: 20030064575
    Abstract: In order to manufacture components of a semiconductor structure, a buffer layer is epitaxially grown onto a well in a substrate. This buffer layer is subsequently removed in the region outside the wells. This measure reduces edge losses because of the conductive, autodoped layer along the boundary area of the substrate with respect to a following epitaxial layer. The components are suitable for high frequency applications.
    Type: Application
    Filed: September 24, 2002
    Publication date: April 3, 2003
    Inventors: Reinhard Losehand, Hubert Werthmann