Patents by Inventor Huchang Zhang

Huchang Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9498898
    Abstract: A cleaning subsystem removes unwanted material, such as glaze, from saw blades used in a semiconductor singulation process. A cleaning module moves radially towards the saw blade and vertically with respect to the plane of the saw blade in order to enable abrasive cleaning blocks of the cleaning module to selectively remove material from either the upper and lower surfaces of the saw blade or the outer edge of the saw blade. The cleaning assembly can remove material from the saw blade at a predetermined time or position during the singulation process or upon detection of load imbalance during the rotation of the saw blade.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Zhijie Wang, Zhigang Bai, Mei Liu, Jiyong Niu, Zhimei Sun, Huchang Zhang
  • Patent number: 9406625
    Abstract: A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 2, 2016
    Assignee: FREESCALE SEMICONDCUTOR, INC.
    Inventors: Zhijie Wang, Zhigang Bai, Jiyong Niu, Dehong Ye, Huchang Zhang
  • Patent number: 9397066
    Abstract: A bond wire feed system has a wire tensioning unit with a chamber that has a wire inlet aperture and a wire outlet aperture. The wire inlet and outlet apertures have centers that are aligned with a central axis of the chamber. A clamp is positioned to receive a bond wire provided from the wire outlet aperture. The clamp has at least two jaws movable relative to each other and arranged to grip the wire to align a central axis of the wire with the central axis of the chamber. The jaws are also movable along the central axis of the wire in order to pull the wire through the wire tensioning unit.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: July 19, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhijie Wang, Zhigang Bai, Huchang Zhang
  • Publication number: 20160155718
    Abstract: A bond wire feed system has a wire tensioning unit with a chamber that has a wire inlet aperture and a wire outlet aperture. The wire inlet and outlet apertures have centers that are aligned with a central axis of the chamber. A clamp is positioned to receive a bond wire provided from the wire outlet aperture. The clamp has at least two jaws movable relative to each other and arranged to grip the wire to align a central axis of the wire with the central axis of the chamber. The jaws are also movable along the central axis of the wire in order to pull the wire through the wire tensioning unit.
    Type: Application
    Filed: April 23, 2015
    Publication date: June 2, 2016
    Inventors: ZHIJIE WANG, Zhigang Bai, Huchang Zhang
  • Patent number: 9252114
    Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.
    Type: Grant
    Filed: November 23, 2014
    Date of Patent: February 2, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
  • Publication number: 20150371957
    Abstract: A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.
    Type: Application
    Filed: November 26, 2014
    Publication date: December 24, 2015
    Inventors: Zhijie Wang, Zhigang Bai, Jiyong Niu, Dehong Ye, Huchang Zhang
  • Publication number: 20150367529
    Abstract: A cleaning subsystem removes unwanted material, such as glaze, from saw blades used in a semiconductor singulation process. A cleaning module moves radially towards the saw blade and vertically with respect to the plane of the saw blade in order to enable abrasive cleaning blocks of the cleaning module to selectively remove material from either the upper and lower surfaces of the saw blade or the outer edge of the saw blade. The cleaning assembly can remove material from the saw blade at a predetermined time or position during the singulation process or upon detection of load imbalance during the rotation of the saw blade.
    Type: Application
    Filed: November 26, 2014
    Publication date: December 24, 2015
    Inventors: Zhijie Wang, Zhigang Bai, Mei Liu, Jiyong Niu, Zhimei Sun, Huchang Zhang
  • Patent number: 9214413
    Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.
    Type: Grant
    Filed: November 23, 2014
    Date of Patent: December 15, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
  • Publication number: 20150243586
    Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.
    Type: Application
    Filed: November 23, 2014
    Publication date: August 27, 2015
    Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
  • Publication number: 20150243623
    Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.
    Type: Application
    Filed: November 23, 2014
    Publication date: August 27, 2015
    Inventors: Zhijie Wang, Zhigang Bai, Aipeng Shu, Yanbo Xu, Huchang Zhang, Fei Zong
  • Patent number: 8735223
    Abstract: A method of forming a semiconductor device includes affixing a die to a heat sink to form a die and heat sink assembly and then placing the die and heat sink assembly on a support element. A semiconductor device includes a die and heat sink assembly disposed on a support element. The die and heat sink assembly is pre-assembled prior to being disposed on the support element.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 27, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Wei Gao, Zhiwei Gong, Dehong Ye, Huchang Zhang
  • Publication number: 20130056861
    Abstract: A method of forming a semiconductor device includes affixing a die to a heat sink to form a die and heat sink assembly and then placing the die and heat sink assembly on a support element. A semiconductor device includes a die and heat sink assembly disposed on a support element. The die and heat sink assembly is pre-assembled prior to being disposed on the support element.
    Type: Application
    Filed: February 16, 2012
    Publication date: March 7, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Wei Gao, Zhiwei Gong, Dehong Ye, Huchang Zhang