Abstract: The present disclosure discloses a GaN-based HEMT device, comprising a gate electrode, a source electrode, and a drain electrode, and further comprising a substrate, a buffer layer, a GaN channel layer, a first barrier layer, a second barrier layer and a dielectric passivation layer, the buffer layer being sequentially stacked from bottom to top, wherein an N-type ion injection region is formed in the GaN channel layer and the first barrier layer, the source electrode and the drain electrode are formed on an upper surface of the N-type ion-implanted region; the gate electrode is formed on an upper surface of the first barrier layer and is located between the source electrode and the drain electrode; and the dielectric passivation layer encircles the gate electrode so as to isolate the gate electrode from the N-type ion-implanted region.

Abstract: The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer.

Abstract: The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer.

Abstract: The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlxY2-xO3 interface passivation layer formed on the group III-V substrate; and a high dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2?x?1.9. The composite gate dielectric layer modifies the Al/Y ratio of the AlxY2-xO3 interface passivation layer, changes the average number of atomic coordination in the AlxY2-xO3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlxY2-xO3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improves tolerance of the dielectric layer on the voltage, and improves the quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.

Abstract: The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlxY2-xO3 interface passivation layer formed onthe group III-V substrate; and a high dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2?x?1.9.The composite gate dielectric layer modifies the AI/Y ratio of the AlxY2-xO3 interface passivation layer, changes the average number of atomic coordination in the AlxY2-xO3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlxY2-xO3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improvestolerance of the dielectric layer on the voltage, and improvesthe quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.