Abstract: A temperature measurement system and method are provided. The temperature measurement system includes: at least one first PN junction element disposed at a first chip to sense a temperature of the first chip; at least one second PN junction element disposed at a second chip to sense a temperature of the second chip; a second temperature measurement circuit electrically connected to the first and second PN junction elements and disposed at the second chip for measuring to obtain a temperature difference value between the first chip and the second chip; a third temperature measurement circuit comprising at least one third PN junction element and disposed at the second chip for measuring to obtain a temperature value of the second chip; and a processing unit for calculating the temperature difference value and the temperature value of the second chip to obtain a temperature value of the first chip.

Abstract: Provided is a measurement system including: a first chip including at least one first PN junction element adapted to sense a temperature of the first chip; and a second chip electrically connected to the first chip to form a first loop including the first PN junction element. The second chip includes a second loop. The second loop includes at least one second PN junction element adapted to sense a temperature of the second chip. The second chip provides multiple currents in the first loop and the second loop to generate voltage signals associated with the temperature of the first chip and the temperature of the second chip according to the first PN junction element and the second PN junction element and thus calculate the temperature difference between the first chip and the second chip. A measurement method applicable to the measurement system is further provided.

Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

Abstract: A semiconductor device is disclosed herein. The semiconductor device includes a routing structure. The routing structure has an intermediate conductive routing layer. The intermediate conductive routing layer includes a first mesh conductive layer formed in a predetermined second region of the semiconductor device and a second mesh conductive layer formed in a predetermined first region of the semiconductor device. The first mesh conductive layer and the second mesh conductive layer are electrically isolated from each other. The intermediate conductive routing layer further includes multiple first conductive islands formed in the predetermined first region and multiple second conductive islands formed in the predetermined second region.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Abstract: LED driving circuit includes a first current source, a second current source, a current sensing circuit, and a control circuit. The first current source, coupled in series with a heat dissipation resistor, provides a first current path to the LED string. The second current source, coupled in parallel with the serially coupled first current source and the heat dissipation resistor, provides a second current path to the LED string. The current sensing circuit is configured to sense a current sense signal representing a current flowing through the LED string. The control circuit is configured to control a current distribution of the first current path and a second current path in response to the current sense signal. When the current sense signal is greater than a threshold, a current flowing through the first current path is larger than a current flowing through the second current path.

Abstract: A LED driving system for driving a LED matrix. The LED driving system includes an interconnection structure having a first surface and a second surface opposite to the first surface and a plurality of driver dies/chips attached to the first surface of the interconnection structure. The LED matrix is divided into a plurality of sub LED matrix sections that are attached to the second surface of the interconnection structure. The interconnection structure is configured to electrically couple each one of the plurality of sub LED matrix sections to a corresponding one driver die/chip in the plurality of driver dies/chips.

Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Abstract: Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

Abstract: An LED driving system for synchronizing two LED driving integrated circuits to drive LED strings. The LED driving system sequentially activates the LED strings driven by the first LED driving integrated circuit and then outputs a downstream enabling signal from the first LED driving integrated circuit to the second LED driving integrated circuit to activate the LED strings driven by the second LED driving integrated circuit.

Abstract: A LED driving system for driving a LED matrix. The LED driving system includes an interconnection structure having a first surface and a second surface opposite to the first surface and a plurality of driver dies/chips attached to the first surface of the interconnection structure. The LED matrix is divided into a plurality of sub LED matrix sections that are attached to the second surface of the interconnection structure. The interconnection structure is configured to electrically couple each one of the plurality of sub LED matrix sections to a corresponding one driver die/chip in the plurality of driver dies/chips.

Abstract: The description relates to diversified hybrid image annotation for annotating images. One implementation includes generating first image annotations for a query image using a retrieval-based image annotation technique. Second image annotations can be generated for the query image using a model-based image annotation technique. The first and second image annotations can be integrated to generate a diversified hybrid image annotation result for the query image.

Abstract: A feedback control circuit in an LED driving circuit for driving a plurality of LED strings. Each LED string provides a headroom detecting voltage. The feedback control circuit has a status detecting circuit, a counting circuit and a modulating circuit. The status detecting circuit compares each headroom detecting voltage with a low headroom threshold voltage and a high headroom threshold voltage and generates an up self-status signal and a down self-status signal. The counting circuit counts or keeps unchanged and then generates a counting signal based on the up self-status signal and the down self-status signal. The modulating circuit generates a modulating signal based on the counting signal. And based on the modulating signal, the feedback control circuit generates a feedback control signal to regulate a bias voltage supplying the plurality of LED strings.

Abstract: An LED driving system with a master-slave architecture. The LED driving system has at least two LED driving circuits which both have a first status detecting circuit, a second status detecting circuit and a first feedback control circuit. The first status detecting circuit receives a plurality of headroom detecting voltages provided by a plurality of LED strings and generates at least one self-status signal. The second status detecting circuit receives a downstream feedback signal and generates at least one downstream status signal. The first feedback control circuit generates a first feedback control signal based on the at least one self-status signal and the at least one downstream status signal. The second status detecting circuit of one LED driving circuit is coupled to the first feedback control circuit of the other LED driving circuit.

Abstract: The present concepts relate to matching data of two different modalities using two stages of attention. First data is encoded as a set of first vectors representing components of the first data, and second data is encoded as a set of second vectors representing components of the second data. In the first stage, the components of the first data are attended by comparing the first vectors and the second vectors to generate a set of attended vectors. In the second stage, the components of the second data are attended by comparing the second vectors and the attended vectors to generate a plurality of relevance scores. Then, the relevance scores are pooled to calculate a similarity score that indicates a degree of similarity between the first data and the second data.