Patents by Inventor Huei Lin

Huei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12176361
    Abstract: A method of detecting electromagnetic radiation includes illuminating a photodiode of a pixel sensor with electromagnetic radiation, using vertical gate structures of a transfer transistor to couple a cathode of the photodiode to an internal node of the pixel sensor, thereby generating an internal node voltage level, and generating an output voltage level of the pixel sensor based on the internal node voltage level.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Huei Lin, Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Chun-Wei Chia
  • Publication number: 20240421157
    Abstract: A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region to improve carrier mobility, thereby increasing drive strength. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region to further improve carrier mobility. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Xia Li, Ming-Huei Lin, Haining Yang
  • Publication number: 20240404872
    Abstract: Disclosed are devices that include a direct N/P local interconnect with minimal recess on shallow trench isolation (STI) oxide. This reduces undesirable coupling capacitance with active gate, which in turn improves AC performance of the device. Pull or even partial replacement of STI oxide with low-k dielectric can further reduce coupling capacitance.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Inventors: Junjing BAO, Haining YANG, Ming-Huei LIN
  • Publication number: 20240379492
    Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin
  • Publication number: 20240363690
    Abstract: Gate-all-around (GAA) field-effect transistor (FET) device employing strain material structure in inactive gate region(s) of a gate for applying channel strain to the channel(s) of the GAA FET for increased carrier mobility. The GAA FET device includes a GAA P-type (P) FET (PFET) and a GAA N-type (N) FET (NFET) served by a gate with a strain material in the inactive gate region(s) of the gate adjacent to the active gates of the GAA NFET and GAA PFET. In this manner, the strain material applies strain to both the GAA NFET and GAA PFET channels in the elongated direction of the gate in a direction orthogonal to their channel directions between the respective sources and drains, so that a strain material of the same strain type can be used to increase carrier mobility of both the GAA NFET and GAA PFET alike.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 31, 2024
    Inventors: Haining Yang, Ming-Huei Lin, Junjing Bao
  • Patent number: 12132011
    Abstract: An integrated circuit device includes a substrate; an integrated circuit region on the substrate, said integrated circuit region comprising a dielectric stack; a seal ring disposed in said dielectric stack and around a periphery of the integrated circuit region; a trench around the seal ring and exposing a sidewall of the dielectric stack; and a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: October 29, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin, Chu-Chun Chang
  • Patent number: 12132344
    Abstract: An electronic device includes a fuel cell, a first switch, a rechargeable battery, a second switch, and a relay. The fuel cell provides a fuel voltage. The first switch provides the fuel voltage to a first node according to a first control signal. The rechargeable battery provides a battery voltage. The second switch is coupled to the first node and charges the rechargeable battery with the fuel voltage according to a second control signal. The relay provides a voltage of the first node to the load according to the third control signal.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: October 29, 2024
    Assignee: CHUNG-HSIN ELECTRIC &MACHINERY MFG. CORP.
    Inventors: Che-Jung Hsu, Cheng-Huei Lin, Yen-Teh Shih, Yu-Kai Chen, Min-Min Wu
  • Patent number: 12131976
    Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 29, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin
  • Publication number: 20240316127
    Abstract: A method for increasing calcium absorption includes administering to a subject in need thereof a composition containing a culture of Bifidobacterium animalis subsp. lactis CP-9. The Bifidobacterium animalis subsp. lactis CP-9 is deposited under the Budapest Treaty at the China Center for Type Culture Collection (CCTCC) under an accession number CCTCC M 2014588.
    Type: Application
    Filed: November 20, 2023
    Publication date: September 26, 2024
    Inventors: Hsieh-Hsun HO, Yi-Wei KUO, Jui-Fen CHEN, Chi-Huei LIN, Shin-Yu TSAI, Ko-Chiang HSIA
  • Publication number: 20240321861
    Abstract: A logic circuit includes a first circuit having a first diffusion region and a second diffusion region and a second circuit having a third diffusion region, and a fourth diffusion region. First devices in the first circuit each include a portion of the first diffusion region and a portion of the second diffusion region. Second devices in the second circuit each include portions of the third and fourth diffusion regions. The first diffusion region is between the second diffusion region and the third diffusion region. The third diffusion region is between the first diffusion region and the fourth diffusion region. A second distance from a first side of the fourth diffusion region to a second side of the third diffusion region is less than a first distance from a first side of the first diffusion region to a second side of the second diffusion region.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Inventors: Haining Yang, Hyunwoo Park, Ming-Huei Lin, Junjing Bao
  • Publication number: 20240321965
    Abstract: Disclosed are devices that include a contact for electrical connection with a source/drain. The contact occupies a full width of a contact well other than areas occupied by sidewall spacers. As a result, high resistivity (due to the presence of liners and nucleation layers within the contact well in conventional devices) is reduced or eliminated.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Inventors: Junjing BAO, Xia LI, Chih-Sung YANG, Kwanyong LIM, Ming-Huei LIN, Hyunwoo PARK, Haining YANG
  • Publication number: 20240316126
    Abstract: A method for increasing calcium absorption includes use of a composition containing a culture of Bifidobacterium longum subsp. infantis BLI-02 which is deposited under the Budapest Treaty at the China General Microbiological Culture Collection Center (CGMCC) under an accession number CGMCC 15212.
    Type: Application
    Filed: August 21, 2023
    Publication date: September 26, 2024
    Inventors: Hsieh-Hsun HO, Yi-Wei KUO, Jui-Fen CHEN, Chi-Huei LIN, Shin-Yu TSAI, Ko-Chiang HSIA
  • Patent number: 12087712
    Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.
    Type: Grant
    Filed: March 19, 2023
    Date of Patent: September 10, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin, Chu-Chun Chang
  • Publication number: 20240293530
    Abstract: Disclosed herein are multivalent nanoparticle vaccine compositions suitable for use in influenza vaccines. The nanoparticles include effective amounts of influenza glycoproteins that provide increased immune responses compared to a commercially available influenza vaccine composition. The present disclosure also provides vaccine formulation strategies that are cost effective and are convenient for clinical use. Methods of administering the nanoparticle vaccine compositions to a subject are also disclosed.
    Type: Application
    Filed: January 3, 2024
    Publication date: September 5, 2024
    Inventors: Sarathi BODDAPATI, Anushree HERWADKAR, Jason WONG, Yen-Huei LIN, Gale SMITH, Jing-Hui TIAN
  • Publication number: 20240261476
    Abstract: The present invention uses the natural polymer alginate, as an example, to cross-link with Thioglycolic acid to form a sulfur polymer gel called Thiolated Alginate (TA). Thiolated alginate (TA) utilizes the redox reaction of the mucous membrane to the sulfur group, so that its materials can be covalently bonded by disulfide bonds, so as to prolong the residence time of the materials in the intestinal tract, at the same time, to form a thin film in the intestinal tract to reduce energy intake and achieve the effect of preventing or controlling obesity.
    Type: Application
    Filed: December 5, 2023
    Publication date: August 8, 2024
    Inventors: Feng-Huei LIN, Tzu-Chien CHEN, Rui-Chian TANG
  • Publication number: 20240266217
    Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate structure disposed on a substrate, a gate spacer adjacent to the gate structure, a source/drain structure adjacent to the gate spacer, a first dielectric layer disposed on the substrate and the source/drain structure, an etch stop spacer over the first dielectric layer and adjacent to the gate spacer, and an etch stop layer over the gate structure, the gate spacer, and the etch stop spacer. The semiconductor structure further includes a source/drain contact extending through the etch stop layer and the first dielectric layer and in contact with the source/drain structure, a sidewall of the source/drain contact adjoining a sidewall of the etch stop layer and a sidewall of the etch stop spacer.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 8, 2024
    Inventors: Junjing BAO, Haining YANG, Hyunwoo PARK, Kwanyong LIM, Ming-Huei LIN
  • Publication number: 20240238777
    Abstract: Provided herein is a kit for isolation of platelet-rich plasma, comprising a first isolation tube and a second isolation tube. The first isolation tube comprises a first opening and a second opening, and the second isolation tube comprises a first portion, a second portion, and a filter, wherein the first portion has a third opening, the filter is disposed between the first portion and the second portion, the second opening has a diameter in a range of 1 to 5 mm and the filter has a pore size in a range of 1.5 to 4 ?m.
    Type: Application
    Filed: February 9, 2024
    Publication date: July 18, 2024
    Applicant: KARTIGEN BIOMEDICAL INC.
    Inventors: Hwa-Chang LIU, Feng-Huei LIN, Chun-Che YEN
  • Publication number: 20240243131
    Abstract: A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region. The FinFET further includes a second fin structure on the substrate and extending through the STI region. The FinFET also includes a metal gate on the STI region, on the first fin structure, and on the second fin structure. The metal gate is composed of a first sub-metal gate cut line filled with a first stressor material, and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.
    Type: Application
    Filed: January 18, 2023
    Publication date: July 18, 2024
    Inventors: Ming-Huei LIN, Haining YANG, Junjing BAO
  • Publication number: 20240203785
    Abstract: A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 20, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Ching-Pin Hsu, Shih Hung Yang, Chu Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 12005091
    Abstract: The present invention discloses a method for maintaining or improving gastrointestinal condition, which includes: administering a lactic acid bacterial composition to a subject in need thereof, wherein the lactic acid bacterial composition comprises: a Lactobacillus paracasei ET-66 strain with a deposition number CGMCC 13514. The present invention also discloses a method for maintaining or improving gastrointestinal condition, which includes: administering a lactic acid bacterial fermentation composition to a subject in need thereof, wherein the lactic acid bacterial fermentation composition comprises: a fermentation product of a Lactobacillus paracasei ET-66 strain.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: June 11, 2024
    Assignee: GLAC BIOTECH CO., LTD
    Inventors: Hsieh-Hsun Ho, Wen-Yang Lin, Jui-Fen Chen, Yi-Wei Kuo, Jia-Hung Lin, Chi-Huei Lin, Ching-Wei Chen, Yu-Fen Huang