Patents by Inventor Huei-Ping Hsieh

Huei-Ping Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making IC capacitor
    Patent number: 6677216
    Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: January 13, 2004
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chun-Pey Cho, Tsai-Sen Lin, Chou-Shin Jou, Chuan-Yi Wang, Jen-Chieh Chang, Yi-Fu Chung, Huei-Ping Hsieh
  • Method of making IC capacitor
    Publication number: 20030068868
    Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.
    Type: Application
    Filed: October 1, 2002
    Publication date: April 10, 2003
    Applicant: MOSEL VITELIC, INC.
    Inventors: Chun-Pey Cho, Tsai-Sen Lin, Chou-Shin Jou, Chuan-Yi Wang, Jen-Chieh Chang, Yi-Fu Chung, Huei-Ping Hsieh