Abstract: A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is lower than a top surface of the substrate, depositing a gate electrode layer over the substrate and patterning the gate electrode layer to form a first gate electrode region and a second gate electrode region, wherein the second gate electrode region is vertically aligned with the first isolation region and the first gate electrode region is immediately adjacent to the second gate electrode region.

Abstract: A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is lower than a top surface of the substrate, depositing a gate electrode layer over the substrate and patterning the gate electrode layer to form a first gate electrode region and a second gate electrode region, wherein the second gate electrode region is vertically aligned with the first isolation region and the first gate electrode region is immediately adjacent to the second gate electrode region.

Abstract: A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the substrate, removing an upper portion of the first isolation region to form a recess, depositing a gate dielectric layer over the first isolation region, forming a gate electrode layer over the gate dielectric layer and patterning the gate electrode layer to form a gate electrode region, wherein a first portion of the gate electrode region is vertically aligned with the first isolation region and a second portion of the gate electrode region is formed over the substrate, and where a top surface of the first portion is lower than a top surface of the second portion.

Abstract: A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the substrate, removing an upper portion of the first isolation region to form a recess, depositing a gate dielectric layer over the first isolation region, forming a gate electrode layer over the gate dielectric layer and patterning the gate electrode layer to form a gate electrode region, wherein a first portion of the gate electrode region is vertically aligned with the first isolation region and a second portion of the gate electrode region is formed over the substrate, and where a top surface of the first portion is lower than a top surface of the second portion.

Abstract: A device includes a plurality of isolation regions formed in a substrate, wherein a top surface of a first isolation region is lower than a top surface of the substrate and a second isolation region has a first portion in a high voltage region and a second portion in a low voltage region, a first gate electrode layer over the high voltage region, a second gate electrode layer over the second isolation region and a third gate electrode layer over the low voltage region, wherein a bottom surface of the first gate electrode layer is higher than a bottom surface of the third gate electrode layer.

Abstract: A device includes a plurality of isolation regions formed in a substrate, wherein a top surface of a first isolation region is lower than a top surface of the substrate and a second isolation region has a first portion in a high voltage region and a second portion in a low voltage region, a first gate electrode layer over the high voltage region, a second gate electrode layer over the second isolation region and a third gate electrode layer over the low voltage region, wherein a bottom surface of the first gate electrode layer is higher than a bottom surface of the third gate electrode layer.

Abstract: A lateral MOSFET comprises a plurality of isolation regions formed in a substrate, wherein a first isolation region is of a top surface lower than a top surface of the substrate. The lateral MOSFET further includes a gate electrode layer having a first gate electrode layer formed over the first isolation region and a second gate electrode layer formed over the top surface of the substrate, wherein a top surface of the first gate electrode layer is lower than a top surface of the second gate electrode layer.

Abstract: Dummy structures between a high voltage (HV) region and a low voltage (LV) region of a substrate are disclosed, along with methods of forming the dummy structures. An embodiment is a structure comprising a HV gate dielectric over a HV region of a substrate, a LV gate dielectric over a LV region of the substrate, and a dummy structure over a top surface of the HV gate dielectric. A thickness of the LV gate dielectric is less than a thickness of the HV gate dielectric. The dummy structure is on a sidewall of the HV gate dielectric.

Abstract: A lateral MOSFET comprises a plurality of isolation regions formed in a substrate, wherein a first isolation region is of a top surface lower than a top surface of the substrate. The lateral MOSFET further comprises a gate electrode layer having a first gate electrode layer formed over the first isolation region and a second gate electrode layer formed over the top surface of the substrate, wherein a top surface of the first gate electrode layer is lower than a top surface of the second gate electrode layer.

Abstract: Dummy structures between a high voltage (HV) region and a low voltage (LV) region of a substrate are disclosed, along with methods of forming the dummy structures. An embodiment is a structure comprising a HV gate dielectric over a HV region of a substrate, a LV gate dielectric over a LV region of the substrate, and a dummy structure over a top surface of the HV gate dielectric. A thickness of the LV gate dielectric is less than a thickness of the HV gate dielectric. The dummy structure is on a sidewall of the HV gate dielectric.